259 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx10_kiq_set_resources()
278 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx10_kiq_map_queues()
304 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx10_kiq_unmap_queues()
331 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));  in gfx10_kiq_query_status()
403 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v10_0_write_data_to_reg()
416 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v10_0_wait_reg_mem()
457 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v10_0_ring_test_ring()
512 	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);  in gfx_v10_0_ring_test_ib()
929 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v10_0_get_csb_buffer()
932 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v10_0_get_csb_buffer()
940 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v10_0_get_csb_buffer()
953 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));  in gfx_v10_0_get_csb_buffer()
957 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v10_0_get_csb_buffer()
960 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v10_0_get_csb_buffer()
2679 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v10_0_cp_gfx_start()
2682 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v10_0_cp_gfx_start()
2690 						  PACKET3(PACKET3_SET_CONTEXT_REG,  in gfx_v10_0_cp_gfx_start()
2702 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));  in gfx_v10_0_cp_gfx_start()
2706 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v10_0_cp_gfx_start()
2709 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v10_0_cp_gfx_start()
2712 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v10_0_cp_gfx_start()
2727 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v10_0_cp_gfx_start()
4421 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);  in gfx_v10_0_ring_emit_ib_gfx()
4423 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v10_0_ring_emit_ib_gfx()
4468 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v10_0_ring_emit_ib_compute()
4473 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in gfx_v10_0_ring_emit_ib_compute()
4496 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));  in gfx_v10_0_ring_emit_fence()
4540 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v10_0_ring_emit_vm_flush()
4554 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v10_0_ring_emit_fence_kiq()
4563 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v10_0_ring_emit_fence_kiq()
4574 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v10_0_ring_emit_sb()
4608 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v10_0_ring_emit_cntxcntl()
4617 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));  in gfx_v10_0_ring_emit_init_cond_exec()
4690 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));  in gfx_v10_0_ring_emit_ce_meta()
4724 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));  in gfx_v10_0_ring_emit_de_meta()
4746 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));  in gfx_v10_0_ring_emit_tmz()
4754 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));  in gfx_v10_0_ring_emit_rreg()
4782 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v10_0_ring_emit_wreg()
5157 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5209 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5243 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),