88 	uint32_t	hpd;  member
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
227 			       enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_sense()  argument
231 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_sense()
234 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &  in dce_v8_0_hpd_sense()
250 				      enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_set_polarity()  argument
253 	bool connected = dce_v8_0_hpd_sense(adev, hpd);  in dce_v8_0_hpd_set_polarity()
255 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_set_polarity()
258 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_set_polarity()
263 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_set_polarity()
283 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_init()
286 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
288 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
297 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
299 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
303 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
304 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
325 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_fini()
328 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_fini()
330 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);  in dce_v8_0_hpd_fini()
332 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_fini()
3138 	unsigned hpd;  in dce_v8_0_hpd_irq()  local
3145 	hpd = entry->src_data[0];  in dce_v8_0_hpd_irq()
3146 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v8_0_hpd_irq()
3147 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v8_0_hpd_irq()
3150 		tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_irq()
3152 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_irq()
3154 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v8_0_hpd_irq()