1237 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_afmt_audio_select_pin()
1240 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_audio_select_pin()
1241 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v11_0_afmt_audio_select_pin()
1242 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_audio_select_pin()
1256 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_latency_fields()
1284 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_latency_fields()
1299 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_speaker_allocation()
1321 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1334 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1365 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_sad_regs()
1416 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v11_0_audio_write_sad_regs()
1516 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1518 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1519 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1521 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1523 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1525 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1526 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1528 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1530 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1532 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1533 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1535 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1552 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1554 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1556 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1558 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1573 	if (!dig || !dig->afmt)  in dce_v11_0_audio_set_dto()
1606 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_setmode()
1610 	if (!dig->afmt->enabled)  in dce_v11_0_afmt_setmode()
1620 	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);  in dce_v11_0_afmt_setmode()
1621 	dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_setmode()
1625 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1627 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v11_0_afmt_setmode()
1629 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v11_0_afmt_setmode()
1631 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1656 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1658 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1662 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1664 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1669 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1671 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1674 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1676 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1679 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1681 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v11_0_afmt_setmode()
1683 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1688 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1690 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1693 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1695 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1704 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1708 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1710 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1712 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1714 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1716 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1723 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1727 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v11_0_afmt_setmode()
1748 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1753 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1755 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1757 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1759 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1762 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1764 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v11_0_afmt_setmode()
1765 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v11_0_afmt_setmode()
1766 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1767 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1770 	dce_v11_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v11_0_afmt_setmode()
1780 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_enable()
1784 	if (enable && dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1786 	if (!enable && !dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1789 	if (!enable && dig->afmt->pin) {  in dce_v11_0_afmt_enable()
1790 		dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_enable()
1791 		dig->afmt->pin = NULL;  in dce_v11_0_afmt_enable()
1794 	dig->afmt->enabled = enable;  in dce_v11_0_afmt_enable()
1797 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v11_0_afmt_enable()
1805 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_init()
1809 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v11_0_afmt_init()
1810 		if (adev->mode_info.afmt[i]) {  in dce_v11_0_afmt_init()
1811 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v11_0_afmt_init()
1812 			adev->mode_info.afmt[i]->id = i;  in dce_v11_0_afmt_init()
1816 				kfree(adev->mode_info.afmt[j]);  in dce_v11_0_afmt_init()
1817 				adev->mode_info.afmt[j] = NULL;  in dce_v11_0_afmt_init()
1830 		kfree(adev->mode_info.afmt[i]);  in dce_v11_0_afmt_fini()
1831 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_fini()
3463 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v11_0_encoder_prepare()