90 	uint32_t        hpd;  member
96 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
291  * dce_v11_0_hpd_sense - hpd sense callback.
294  * @hpd: hpd (hotplug detect) pin
300 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
304 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_sense()
307 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v11_0_hpd_sense()
315  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
318  * @hpd: hpd (hotplug detect) pin
320  * Set the polarity of the hpd pin (evergreen+).
323 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
326 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
328 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_set_polarity()
331 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_set_polarity()
336 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_set_polarity()
340  * dce_v11_0_hpd_init - hpd setup callback.
344  * Setup the hpd pins used by the card (evergreen+).
345  * Enable the pin, set the polarity, and enable the hpd interrupts.
356 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_init()
361 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v11_0_hpd_init()
366 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
368 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
372 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
374 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
376 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
383 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
385 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
386 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
391  * dce_v11_0_hpd_fini - hpd tear down callback.
395  * Tear down the hpd pins used by the card (evergreen+).
396  * Disable the hpd interrupts.
407 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_fini()
410 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_fini()
412 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_fini()
414 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
2888 	/* HPD hotplug */  in dce_v11_0_sw_init()
2982 	/* initialize hpd */  in dce_v11_0_hw_init()
3138 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3143 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3144 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3150 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3152 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3155 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3157 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3291 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3295 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3296 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3300 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3302 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3379 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3386 	hpd = entry->src_data[0];  in dce_v11_0_hpd_irq()
3387 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3388 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3391 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3393 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()