88 	uint32_t        hpd;  member
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
282 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
286 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_sense()
289 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v10_0_hpd_sense()
305 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
308 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
310 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_set_polarity()
313 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_set_polarity()
318 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_set_polarity()
338 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_init()
348 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
350 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
354 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
356 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
358 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
365 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
367 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
369 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
390 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_fini()
393 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_fini()
395 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_fini()
398 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
3012 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
3017 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
3018 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3024 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3026 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3029 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3031 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3165 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3169 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3170 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3174 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3176 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3252 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3259 	hpd = entry->src_data[0];  in dce_v10_0_hpd_irq()
3260 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3261 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3264 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3266 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()