1211 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_afmt_audio_select_pin()
1214 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_audio_select_pin()
1215 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v10_0_afmt_audio_select_pin()
1216 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_audio_select_pin()
1230 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_latency_fields()
1258 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_latency_fields()
1273 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_speaker_allocation()
1295 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1308 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v10_0_audio_write_speaker_allocation()
1339 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v10_0_audio_write_sad_regs()
1390 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v10_0_audio_write_sad_regs()
1474 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1476 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1477 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1479 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1481 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1483 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1484 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1486 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1488 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1490 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1491 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v10_0_afmt_update_ACR()
1493 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_update_ACR()
1510 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1512 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1514 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1516 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v10_0_afmt_update_avi_infoframe()
1531 	if (!dig || !dig->afmt)  in dce_v10_0_audio_set_dto()
1564 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_setmode()
1568 	if (!dig->afmt->enabled)  in dce_v10_0_afmt_setmode()
1578 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);  in dce_v10_0_afmt_setmode()
1579 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_setmode()
1583 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1585 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v10_0_afmt_setmode()
1587 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v10_0_afmt_setmode()
1589 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1614 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1616 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1620 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1622 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1627 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1629 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1632 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1634 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1637 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1639 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v10_0_afmt_setmode()
1641 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1646 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1648 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1651 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1653 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1662 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1666 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1668 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1670 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1672 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1674 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1681 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1685 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v10_0_afmt_setmode()
1706 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1711 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1713 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1715 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1717 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v10_0_afmt_setmode()
1720 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v10_0_afmt_setmode()
1722 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v10_0_afmt_setmode()
1723 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v10_0_afmt_setmode()
1724 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1725 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v10_0_afmt_setmode()
1728 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v10_0_afmt_setmode()
1738 	if (!dig || !dig->afmt)  in dce_v10_0_afmt_enable()
1742 	if (enable && dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1744 	if (!enable && !dig->afmt->enabled)  in dce_v10_0_afmt_enable()
1747 	if (!enable && dig->afmt->pin) {  in dce_v10_0_afmt_enable()
1748 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v10_0_afmt_enable()
1749 		dig->afmt->pin = NULL;  in dce_v10_0_afmt_enable()
1752 	dig->afmt->enabled = enable;  in dce_v10_0_afmt_enable()
1755 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v10_0_afmt_enable()
1763 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_init()
1767 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v10_0_afmt_init()
1768 		if (adev->mode_info.afmt[i]) {  in dce_v10_0_afmt_init()
1769 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v10_0_afmt_init()
1770 			adev->mode_info.afmt[i]->id = i;  in dce_v10_0_afmt_init()
1774 				kfree(adev->mode_info.afmt[j]);  in dce_v10_0_afmt_init()
1775 				adev->mode_info.afmt[j] = NULL;  in dce_v10_0_afmt_init()
1788 		kfree(adev->mode_info.afmt[i]);  in dce_v10_0_afmt_fini()
1789 		adev->mode_info.afmt[i] = NULL;  in dce_v10_0_afmt_fini()
3337 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v10_0_encoder_prepare()