445 				       struct amdgpu_firmware_info *ucode,  in amdgpu_ucode_init_single_fw()  argument
452 	if (NULL == ucode->fw)  in amdgpu_ucode_init_single_fw()
455 	ucode->mc_addr = mc_addr;  in amdgpu_ucode_init_single_fw()
456 	ucode->kaddr = kptr;  in amdgpu_ucode_init_single_fw()
458 	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)  in amdgpu_ucode_init_single_fw()
461 	header = (const struct common_firmware_header *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
462 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
463 	dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
466 	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&  in amdgpu_ucode_init_single_fw()
467 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&  in amdgpu_ucode_init_single_fw()
468 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&  in amdgpu_ucode_init_single_fw()
469 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&  in amdgpu_ucode_init_single_fw()
470 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&  in amdgpu_ucode_init_single_fw()
471 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&  in amdgpu_ucode_init_single_fw()
472 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&  in amdgpu_ucode_init_single_fw()
473 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&  in amdgpu_ucode_init_single_fw()
474 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {  in amdgpu_ucode_init_single_fw()
475 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);  in amdgpu_ucode_init_single_fw()
477 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
479 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
480 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||  in amdgpu_ucode_init_single_fw()
481 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {  in amdgpu_ucode_init_single_fw()
482 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -  in amdgpu_ucode_init_single_fw()
485 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
487 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
488 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||  in amdgpu_ucode_init_single_fw()
489 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {  in amdgpu_ucode_init_single_fw()
490 		ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;  in amdgpu_ucode_init_single_fw()
492 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
495 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
496 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {  in amdgpu_ucode_init_single_fw()
497 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -  in amdgpu_ucode_init_single_fw()
500 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
502 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
503 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {  in amdgpu_ucode_init_single_fw()
504 		ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);  in amdgpu_ucode_init_single_fw()
506 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
509 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
510 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {  in amdgpu_ucode_init_single_fw()
511 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;  in amdgpu_ucode_init_single_fw()
512 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,  in amdgpu_ucode_init_single_fw()
513 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
514 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {  in amdgpu_ucode_init_single_fw()
515 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;  in amdgpu_ucode_init_single_fw()
516 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,  in amdgpu_ucode_init_single_fw()
517 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
518 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {  in amdgpu_ucode_init_single_fw()
519 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;  in amdgpu_ucode_init_single_fw()
520 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,  in amdgpu_ucode_init_single_fw()
521 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
527 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,  in amdgpu_ucode_patch_jt()  argument
535 	if (NULL == ucode->fw)  in amdgpu_ucode_patch_jt()
538 	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;  in amdgpu_ucode_patch_jt()
539 	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_patch_jt()
540 	dst_addr = ucode->kaddr +  in amdgpu_ucode_patch_jt()
543 	src_addr = (uint8_t *)ucode->fw->data +  in amdgpu_ucode_patch_jt()
581 	struct amdgpu_firmware_info *ucode = NULL;  in amdgpu_ucode_init_bo()  local
600 		ucode = &adev->firmware.ucode[i];  in amdgpu_ucode_init_bo()
601 		if (ucode->fw) {  in amdgpu_ucode_init_bo()
602 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,  in amdgpu_ucode_init_bo()
607 				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_init_bo()
608 				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,  in amdgpu_ucode_init_bo()
612 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);  in amdgpu_ucode_init_bo()