81 static int __update_table_header(struct amdgpu_ras_eeprom_control *control,  in __update_table_header()  argument
94 	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);  in __update_table_header()
96 	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);  in __update_table_header()
103 static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
105 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_init()  argument
108 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
110 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
118 	mutex_init(&control->tbl_mutex);  in amdgpu_ras_eeprom_init()
122 		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);  in amdgpu_ras_eeprom_init()
135 	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);  in amdgpu_ras_eeprom_init()
144 		control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /  in amdgpu_ras_eeprom_init()
147 				 control->num_recs);  in amdgpu_ras_eeprom_init()
159 		ret = __update_table_header(control, buff);  in amdgpu_ras_eeprom_init()
168 void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_fini()  argument
170 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_fini()
174 		smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);  in amdgpu_ras_eeprom_fini()
182 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buff()  argument
209 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buff()  argument
270 static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
276 	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)  in __calc_hdr_byte_sum()
277 		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);  in __calc_hdr_byte_sum()
300 static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,  in __calc_tbl_byte_sum()  argument
303 	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);  in __calc_tbl_byte_sum()
307 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,  in __update_tbl_checksum()  argument
319 	control->tbl_byte_sum -= old_hdr_byte_sum;  in __update_tbl_checksum()
320 	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);  in __update_tbl_checksum()
322 	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);  in __update_tbl_checksum()
326 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,  in __validate_tbl_checksum()  argument
329 	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);  in __validate_tbl_checksum()
331 	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {  in __validate_tbl_checksum()
332 		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);  in __validate_tbl_checksum()
339 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_process_recods()  argument
347 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_process_recods()
357 	mutex_lock(&control->tbl_mutex);  in amdgpu_ras_eeprom_process_recods()
366 	if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))  in amdgpu_ras_eeprom_process_recods()
367 		control->next_addr = EEPROM_RECORD_START;  in amdgpu_ras_eeprom_process_recods()
380 		control->next_addr = __correct_eeprom_dest_address(control->next_addr);  in amdgpu_ras_eeprom_process_recods()
387 			       ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);  in amdgpu_ras_eeprom_process_recods()
393 		buff[0] = ((control->next_addr >> 8) & 0xff);  in amdgpu_ras_eeprom_process_recods()
394 		buff[1] = (control->next_addr & 0xff);  in amdgpu_ras_eeprom_process_recods()
398 			__encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);  in amdgpu_ras_eeprom_process_recods()
404 		control->next_addr += EEPROM_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_process_recods()
407 	ret = i2c_transfer(&control->eeprom_accessor, msgs, num);  in amdgpu_ras_eeprom_process_recods()
421 			__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);  in amdgpu_ras_eeprom_process_recods()
426 		uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_process_recods()
435 		control->num_recs += num;  in amdgpu_ras_eeprom_process_recods()
436 		control->num_recs %= EEPROM_MAX_RECORD_NUM;  in amdgpu_ras_eeprom_process_recods()
437 		control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;  in amdgpu_ras_eeprom_process_recods()
438 		if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)  in amdgpu_ras_eeprom_process_recods()
439 			control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_process_recods()
440 			control->num_recs * EEPROM_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_process_recods()
442 		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);  in amdgpu_ras_eeprom_process_recods()
444 		__update_table_header(control, buffs);  in amdgpu_ras_eeprom_process_recods()
445 	} else if (!__validate_tbl_checksum(control, records, num)) {  in amdgpu_ras_eeprom_process_recods()
457 	mutex_unlock(&control->tbl_mutex);  in amdgpu_ras_eeprom_process_recods()
464 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
477 	if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
481 		control->next_addr = EEPROM_RECORD_START;
483 		if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {