108 		ret = smu_read_sensor(&adev->smu, sensor, data, size);  in amdgpu_dpm_read_sensor()
163 		if (adev->smu.ppt_funcs->get_current_power_state)  in amdgpu_get_dpm_state()
294 		level = smu_get_performance_level(&adev->smu);  in amdgpu_get_dpm_forced_performance_level()
365 		current_level = smu_get_performance_level(&adev->smu);  in amdgpu_set_dpm_forced_performance_level()
383 		ret = smu_force_performance_level(&adev->smu, level);  in amdgpu_set_dpm_forced_performance_level()
415 		ret = smu_get_power_num_states(&adev->smu, &data);  in amdgpu_get_pp_num_states()
439 	struct smu_context *smu = &adev->smu;  in amdgpu_get_pp_cur_state()  local
444 		pm = smu_get_current_power_state(smu);  in amdgpu_get_pp_cur_state()
445 		ret = smu_get_power_num_states(smu, &data);  in amdgpu_get_pp_cur_state()
539 		size = smu_sys_get_pp_table(&adev->smu, (void **)&table);  in amdgpu_get_pp_table()
566 		ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);  in amdgpu_set_pp_table()
693 		ret = smu_od_edit_dpm_table(&adev->smu, type,  in amdgpu_set_pp_od_clk_voltage()
730 		size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);  in amdgpu_get_pp_od_clk_voltage()
731 		size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);  in amdgpu_get_pp_od_clk_voltage()
732 		size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);  in amdgpu_get_pp_od_clk_voltage()
733 		size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);  in amdgpu_get_pp_od_clk_voltage()
780 		ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);  in amdgpu_set_pp_feature_status()
800 		return smu_sys_get_pp_feature_mask(&adev->smu, buf);  in amdgpu_get_pp_feature_status()
844 		return smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);  in amdgpu_get_pp_dpm_sclk()
905 		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);  in amdgpu_set_pp_dpm_sclk()
927 		return smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);  in amdgpu_get_pp_dpm_mclk()
952 		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);  in amdgpu_set_pp_dpm_mclk()
970 		return smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);  in amdgpu_get_pp_dpm_socclk()
992 		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);  in amdgpu_set_pp_dpm_socclk()
1010 		return smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);  in amdgpu_get_pp_dpm_fclk()
1032 		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);  in amdgpu_set_pp_dpm_fclk()
1050 		return smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);  in amdgpu_get_pp_dpm_dcefclk()
1072 		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);  in amdgpu_set_pp_dpm_dcefclk()
1090 		return smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);  in amdgpu_get_pp_dpm_pcie()
1112 		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);  in amdgpu_set_pp_dpm_pcie()
1131 		value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);  in amdgpu_get_pp_sclk_od()
1156 		value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);  in amdgpu_set_pp_sclk_od()
1182 		value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);  in amdgpu_get_pp_mclk_od()
1207 		value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);  in amdgpu_set_pp_mclk_od()
1252 		return smu_get_power_profile_mode(&adev->smu, buf);  in amdgpu_get_pp_power_profile_mode()
1304 		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);  in amdgpu_set_pp_power_profile_mode()
1602 		pwm_mode = smu_get_fan_control_mode(&adev->smu);  in amdgpu_hwmon_get_pwm1_enable()
1632 		smu_set_fan_control_mode(&adev->smu, value);  in amdgpu_hwmon_set_pwm1_enable()
1671 		pwm_mode = smu_get_fan_control_mode(&adev->smu);  in amdgpu_hwmon_set_pwm1()
1686 		err = smu_set_fan_speed_percent(&adev->smu, value);  in amdgpu_hwmon_set_pwm1()
1712 		err = smu_get_fan_speed_percent(&adev->smu, &speed);  in amdgpu_hwmon_get_pwm1()
1740 		err = smu_get_fan_speed_rpm(&adev->smu, &speed);  in amdgpu_hwmon_get_fan1_input()
1800 		err = smu_get_fan_speed_rpm(&adev->smu, &rpm);  in amdgpu_hwmon_get_fan1_target()
1822 		pwm_mode = smu_get_fan_control_mode(&adev->smu);  in amdgpu_hwmon_set_fan1_target()
1839 		err = smu_set_fan_speed_rpm(&adev->smu, value);  in amdgpu_hwmon_set_fan1_target()
1859 		pwm_mode = smu_get_fan_control_mode(&adev->smu);  in amdgpu_hwmon_get_fan1_enable()
1897 		smu_set_fan_control_mode(&adev->smu, pwm_mode);  in amdgpu_hwmon_set_fan1_enable()
2013 		smu_get_power_limit(&adev->smu, &limit, true);  in amdgpu_hwmon_show_power_cap_max()
2031 		smu_get_power_limit(&adev->smu, &limit, false);  in amdgpu_hwmon_show_power_cap()
2058 		err = smu_set_power_limit(&adev->smu, value);  in amdgpu_hwmon_set_power_cap()
2665 	    ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);  in amdgpu_dpm_enable_uvd()
2692 	    ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);  in amdgpu_dpm_enable_vce()
2878 	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||  in amdgpu_pm_sysfs_init()
2974 	if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||  in amdgpu_pm_sysfs_fini()
3008 		struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;  in amdgpu_pm_compute_clocks()
3009 		smu_handle_task(&adev->smu,  in amdgpu_pm_compute_clocks()