Lines Matching defs:amdgpu_crtc

380 struct amdgpu_crtc {  struct
381 	struct drm_crtc base;
382 	int crtc_id;
383 	bool enabled;
384 	bool can_tile;
385 	uint32_t crtc_offset;
386 	struct drm_gem_object *cursor_bo;
387 	uint64_t cursor_addr;
388 	int cursor_x;
389 	int cursor_y;
390 	int cursor_hot_x;
391 	int cursor_hot_y;
392 	int cursor_width;
393 	int cursor_height;
394 	int max_cursor_width;
395 	int max_cursor_height;
396 	enum amdgpu_rmx_type rmx_type;
397 	u8 h_border;
398 	u8 v_border;
399 	fixed20_12 vsc;
400 	fixed20_12 hsc;
401 	struct drm_display_mode native_mode;
402 	u32 pll_id;
404 	struct amdgpu_flip_work *pflip_works;
405 	enum amdgpu_flip_status pflip_status;
406 	int deferred_flip_completion;
407 	u32 last_flip_vblank;
409 	struct amdgpu_atom_ss ss;
410 	bool ss_enabled;
411 	u32 adjusted_clock;
412 	int bpc;
413 	u32 pll_reference_div;
414 	u32 pll_post_div;
415 	u32 pll_flags;
416 	struct drm_encoder *encoder;
417 	struct drm_connector *connector;
419 	u32 line_time;
420 	u32 wm_low;
421 	u32 wm_high;
422 	u32 lb_vblank_lead_lines;
423 	struct drm_display_mode hw_mode;
425 	struct hrtimer vblank_timer;
426 	enum amdgpu_interrupt_state vsync_timer_enabled;
428 	int otg_inst;
429 	struct drm_pending_vblank_event *event;