Lines Matching refs:amdgpu_device

187 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
188 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
190 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
192 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
195 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
198 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
200 	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
201 	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
349 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
350 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
355 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
362 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
363 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
366 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
368 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
369 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
370 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
372 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
373 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
375 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
377 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
379 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
381 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
383 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
385 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
387 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);