Lines Matching full:chip
95 struct ioh_gpio *chip = gpiochip_get_data(gpio); in ioh_gpio_set() local
98 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
106 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_set()
111 struct ioh_gpio *chip = gpiochip_get_data(gpio); in ioh_gpio_get() local
113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr)); in ioh_gpio_get()
119 struct ioh_gpio *chip = gpiochip_get_data(gpio); in ioh_gpio_direction_output() local
124 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_output()
125 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_output()
126 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_output()
128 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_output()
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
137 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_output()
144 struct ioh_gpio *chip = gpiochip_get_data(gpio); in ioh_gpio_direction_input() local
148 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_input()
149 pm = ioread32(&chip->reg->regs[chip->ch].pm) & in ioh_gpio_direction_input()
150 ((1 << num_ports[chip->ch]) - 1); in ioh_gpio_direction_input()
152 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_input()
153 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_input()
162 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip) in ioh_gpio_save_reg_conf() argument
166 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_save_reg_conf()
167 chip->ioh_gpio_reg.po_reg = in ioh_gpio_save_reg_conf()
168 ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_save_reg_conf()
169 chip->ioh_gpio_reg.pm_reg = in ioh_gpio_save_reg_conf()
170 ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_save_reg_conf()
171 chip->ioh_gpio_reg.ien_reg = in ioh_gpio_save_reg_conf()
172 ioread32(&chip->reg->regs[chip->ch].ien); in ioh_gpio_save_reg_conf()
173 chip->ioh_gpio_reg.imask_reg = in ioh_gpio_save_reg_conf()
174 ioread32(&chip->reg->regs[chip->ch].imask); in ioh_gpio_save_reg_conf()
175 chip->ioh_gpio_reg.im0_reg = in ioh_gpio_save_reg_conf()
176 ioread32(&chip->reg->regs[chip->ch].im_0); in ioh_gpio_save_reg_conf()
177 chip->ioh_gpio_reg.im1_reg = in ioh_gpio_save_reg_conf()
178 ioread32(&chip->reg->regs[chip->ch].im_1); in ioh_gpio_save_reg_conf()
180 chip->ioh_gpio_reg.use_sel_reg = in ioh_gpio_save_reg_conf()
181 ioread32(&chip->reg->ioh_sel_reg[i]); in ioh_gpio_save_reg_conf()
188 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip) in ioh_gpio_restore_reg_conf() argument
192 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_restore_reg_conf()
193 iowrite32(chip->ioh_gpio_reg.po_reg, in ioh_gpio_restore_reg_conf()
194 &chip->reg->regs[chip->ch].po); in ioh_gpio_restore_reg_conf()
195 iowrite32(chip->ioh_gpio_reg.pm_reg, in ioh_gpio_restore_reg_conf()
196 &chip->reg->regs[chip->ch].pm); in ioh_gpio_restore_reg_conf()
197 iowrite32(chip->ioh_gpio_reg.ien_reg, in ioh_gpio_restore_reg_conf()
198 &chip->reg->regs[chip->ch].ien); in ioh_gpio_restore_reg_conf()
199 iowrite32(chip->ioh_gpio_reg.imask_reg, in ioh_gpio_restore_reg_conf()
200 &chip->reg->regs[chip->ch].imask); in ioh_gpio_restore_reg_conf()
201 iowrite32(chip->ioh_gpio_reg.im0_reg, in ioh_gpio_restore_reg_conf()
202 &chip->reg->regs[chip->ch].im_0); in ioh_gpio_restore_reg_conf()
203 iowrite32(chip->ioh_gpio_reg.im1_reg, in ioh_gpio_restore_reg_conf()
204 &chip->reg->regs[chip->ch].im_1); in ioh_gpio_restore_reg_conf()
206 iowrite32(chip->ioh_gpio_reg.use_sel_reg, in ioh_gpio_restore_reg_conf()
207 &chip->reg->ioh_sel_reg[i]); in ioh_gpio_restore_reg_conf()
214 struct ioh_gpio *chip = gpiochip_get_data(gpio); in ioh_gpio_to_irq() local
215 return chip->irq_base + offset; in ioh_gpio_to_irq()
218 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port) in ioh_gpio_setup() argument
220 struct gpio_chip *gpio = &chip->gpio; in ioh_gpio_setup()
222 gpio->label = dev_name(chip->dev); in ioh_gpio_setup()
246 struct ioh_gpio *chip = gc->private; in ioh_irq_type() local
248 ch = irq - chip->irq_base; in ioh_irq_type()
249 if (irq <= chip->irq_base + 7) { in ioh_irq_type()
250 im_reg = &chip->reg->regs[chip->ch].im_0; in ioh_irq_type()
253 im_reg = &chip->reg->regs[chip->ch].im_1; in ioh_irq_type()
256 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", in ioh_irq_type()
259 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_type()
280 dev_warn(chip->dev, "%s: unknown type(%dd)", in ioh_irq_type()
290 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); in ioh_irq_type()
293 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_type()
296 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_type()
297 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); in ioh_irq_type()
299 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_type()
307 struct ioh_gpio *chip = gc->private; in ioh_irq_unmask() local
309 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_unmask()
310 &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_unmask()
316 struct ioh_gpio *chip = gc->private; in ioh_irq_mask() local
318 iowrite32(1 << (d->irq - chip->irq_base), in ioh_irq_mask()
319 &chip->reg->regs[chip->ch].imask); in ioh_irq_mask()
325 struct ioh_gpio *chip = gc->private; in ioh_irq_disable() local
329 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_disable()
330 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
331 ien &= ~(1 << (d->irq - chip->irq_base)); in ioh_irq_disable()
332 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
333 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_disable()
339 struct ioh_gpio *chip = gc->private; in ioh_irq_enable() local
343 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_enable()
344 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
345 ien |= 1 << (d->irq - chip->irq_base); in ioh_irq_enable()
346 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
347 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_enable()
352 struct ioh_gpio *chip = dev_id; in ioh_gpio_handler() local
357 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_handler()
358 reg_val = ioread32(&chip->reg->regs[i].istatus); in ioh_gpio_handler()
361 dev_dbg(chip->dev, in ioh_gpio_handler()
365 &chip->reg->regs[chip->ch].iclr); in ioh_gpio_handler()
366 generic_handle_irq(chip->irq_base + j); in ioh_gpio_handler()
374 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, in ioh_gpio_alloc_generic_chip() argument
382 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start, in ioh_gpio_alloc_generic_chip()
383 chip->base, handle_simple_irq); in ioh_gpio_alloc_generic_chip()
387 gc->private = chip; in ioh_gpio_alloc_generic_chip()
390 ct->chip.irq_mask = ioh_irq_mask; in ioh_gpio_alloc_generic_chip()
391 ct->chip.irq_unmask = ioh_irq_unmask; in ioh_gpio_alloc_generic_chip()
392 ct->chip.irq_set_type = ioh_irq_type; in ioh_gpio_alloc_generic_chip()
393 ct->chip.irq_disable = ioh_irq_disable; in ioh_gpio_alloc_generic_chip()
394 ct->chip.irq_enable = ioh_irq_enable; in ioh_gpio_alloc_generic_chip()
396 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in ioh_gpio_alloc_generic_chip()
408 struct ioh_gpio *chip; in ioh_gpio_probe() local
432 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL); in ioh_gpio_probe()
438 chip = chip_save; in ioh_gpio_probe()
439 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_probe()
440 chip->dev = &pdev->dev; in ioh_gpio_probe()
441 chip->base = base; in ioh_gpio_probe()
442 chip->reg = chip->base; in ioh_gpio_probe()
443 chip->ch = i; in ioh_gpio_probe()
444 spin_lock_init(&chip->spinlock); in ioh_gpio_probe()
445 ioh_gpio_setup(chip, num_ports[i]); in ioh_gpio_probe()
446 ret = gpiochip_add_data(&chip->gpio, chip); in ioh_gpio_probe()
453 chip = chip_save; in ioh_gpio_probe()
454 for (j = 0; j < 8; j++, chip++) { in ioh_gpio_probe()
463 chip->irq_base = irq_base; in ioh_gpio_probe()
465 ret = ioh_gpio_alloc_generic_chip(chip, in ioh_gpio_probe()
471 chip = chip_save; in ioh_gpio_probe()
473 IRQF_SHARED, KBUILD_MODNAME, chip); in ioh_gpio_probe()
480 pci_set_drvdata(pdev, chip); in ioh_gpio_probe()
485 chip = chip_save; in ioh_gpio_probe()
487 gpiochip_remove(&chip->gpio); in ioh_gpio_probe()
488 chip++; in ioh_gpio_probe()
510 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_remove() local
513 chip_save = chip; in ioh_gpio_remove()
515 for (i = 0; i < 8; i++, chip++) in ioh_gpio_remove()
516 gpiochip_remove(&chip->gpio); in ioh_gpio_remove()
518 chip = chip_save; in ioh_gpio_remove()
519 pci_iounmap(pdev, chip->base); in ioh_gpio_remove()
522 kfree(chip); in ioh_gpio_remove()
529 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_suspend() local
532 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_suspend()
533 ioh_gpio_save_reg_conf(chip); in ioh_gpio_suspend()
534 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_suspend()
553 struct ioh_gpio *chip = pci_get_drvdata(pdev); in ioh_gpio_resume() local
566 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_resume()
567 iowrite32(0x01, &chip->reg->srst); in ioh_gpio_resume()
568 iowrite32(0x00, &chip->reg->srst); in ioh_gpio_resume()
569 ioh_gpio_restore_reg_conf(chip); in ioh_gpio_resume()
570 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_resume()