68 	void __iomem *reg_base;  member
84 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
87 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
88 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
100 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
102 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
116 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
118 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
126 	void __iomem *reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get_dir()  local
129 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;  in bcm_kona_gpio_get_dir()
136 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
143 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
152 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
154 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
163 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
170 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
179 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
205 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
210 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
213 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
216 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
227 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
234 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
237 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
240 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
243 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
245 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
266 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
271 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
293 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
304 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
341 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
349 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
352 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
354 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
362 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
370 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
373 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
375 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
384 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
392 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
395 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
397 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
406 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
413 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
438 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
441 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
450 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
463 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
466 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
467 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
477 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
478 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
552 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
555 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
559 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
560 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
561 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
563 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
620 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);  in bcm_kona_gpio_probe()
621 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()