Lines Matching refs:FPGA
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
49 tristate "Altera CvP FPGA Manager"
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
62 tristate "Intel Stratix10 SoC FPGA Manager"
65 FPGA manager driver support for the Intel Stratix10 SoC.
71 FPGA manager driver support for Xilinx FPGA configuration
78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
84 FPGA manager driver support for Lattice MachXO2 configuration
88 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
91 FPGA manager driver support for the Altera Cyclone II FPGA
95 tristate "FPGA Bridge Framework"
101 tristate "Altera SoCFPGA FPGA Bridges"
104 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
108 tristate "Altera FPGA Freeze Bridge"
111 Say Y to enable drivers for Altera FPGA Freeze bridges. A
112 freeze bridge is a bridge that exists in the FPGA fabric to
113 isolate one region of the FPGA from the busses while that
122 The PR Decoupler exists in the FPGA fabric to isolate one
123 region of the FPGA from the busses while that region is
127 tristate "FPGA Region"
130 FPGA Region common code. A FPGA Region controls a FPGA Manager
131 and the FPGA Bridges associated with either a reconfigurable
132 region of an FPGA or a whole FPGA.
135 tristate "FPGA Region Device Tree Overlay Support"
138 Support for loading FPGA images by applying a Device Tree
142 tristate "FPGA Device Feature List (DFL) support"
148 to provide an extensible way of adding features for FPGA.
150 devices (e.g. FPGA Management Engine, Port and Accelerator
151 Function Unit) and their private features for target FPGA devices.
154 Gate Array (FPGA) solutions which implement Device Feature List.
158 tristate "FPGA DFL FME Driver"
161 The FPGA Management Engine (FME) is a feature device implemented
164 FPGA platform level management features. There shall be one FME
165 per DFL based FPGA device.
168 tristate "FPGA DFL FME Manager Driver"
171 Say Y to enable FPGA Manager driver for FPGA Management Engine.
174 tristate "FPGA DFL FME Bridge Driver"
177 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
180 tristate "FPGA DFL FME Region Driver"
183 Say Y to enable FPGA Region driver for FPGA Management Engine.
186 tristate "FPGA DFL AFU Driver"
189 This is the driver for FPGA Accelerated Function Unit (AFU) which
191 to the FPGA infrastructure via a Port. There may be more than one
192 Port/AFU per DFL based FPGA device.
195 tristate "FPGA DFL PCIe Device Driver"
199 Field-Programmable Gate Array (FPGA) solutions which implement
202 FPGA accelerators on the FPGA DFL devices, enables system level
203 management functions such as FPGA partial reconfiguration, power
210 tristate "Xilinx ZynqMP FPGA"
213 FPGA manager driver support for Xilinx ZynqMP FPGAs.
218 endif # FPGA