176 	u64 reg_int;  member
557 	ctx->reg_int = readq(lmc->regs + LMC_INT);  in thunderx_lmc_err_isr()
568 	writeq(ctx->reg_int, lmc->regs + LMC_INT);  in thunderx_lmc_err_isr()
600 			ctx->reg_int);  in thunderx_lmc_threaded_isr()
619 				ctx->reg_int);  in thunderx_lmc_threaded_isr()
623 		if (ctx->reg_int & LMC_INT_UE)  in thunderx_lmc_threaded_isr()
628 		else if (ctx->reg_int & LMC_INT_CE)  in thunderx_lmc_threaded_isr()
1740 	u64  reg_int;  member
1769 	ctx->reg_int = readq(tad->regs + L2C_TAD_INT_W1C);  in thunderx_l2c_tad_isr()
1771 	if (ctx->reg_int & L2C_TAD_INT_ECC) {  in thunderx_l2c_tad_isr()
1774 	} else if (ctx->reg_int & L2C_TAD_INT_TAG) {  in thunderx_l2c_tad_isr()
1777 	} else if (ctx->reg_int & L2C_TAD_INT_LFBTO) {  in thunderx_l2c_tad_isr()
1780 	} else if (ctx->reg_int & L2C_TAD_INT_DISOCI) {  in thunderx_l2c_tad_isr()
1785 	writeq(ctx->reg_int, tad->regs + L2C_TAD_INT_W1C);  in thunderx_l2c_tad_isr()
1801 	ctx->reg_int = readq(cbc->regs + L2C_CBC_INT_W1C);  in thunderx_l2c_cbc_isr()
1803 	if (ctx->reg_int & L2C_CBC_INT_RSD) {  in thunderx_l2c_cbc_isr()
1806 	} else if (ctx->reg_int & L2C_CBC_INT_MIB) {  in thunderx_l2c_cbc_isr()
1809 	} else if (ctx->reg_int & L2C_CBC_INT_IODISOCI) {  in thunderx_l2c_cbc_isr()
1814 	writeq(ctx->reg_int, cbc->regs + L2C_CBC_INT_W1C);  in thunderx_l2c_cbc_isr()
1830 	ctx->reg_int = readq(mci->regs + L2C_MCI_INT_W1C);  in thunderx_l2c_mci_isr()
1833 	writeq(ctx->reg_int, mci->regs + L2C_MCI_INT_W1C);  in thunderx_l2c_mci_isr()
1894 			 l2c->edac_dev->ctl_name, reg_int_name, ctx->reg_int,  in thunderx_l2c_threaded_isr()
1897 		decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx->reg_int);  in thunderx_l2c_threaded_isr()
1901 		if (ctx->reg_int & mask_ue)  in thunderx_l2c_threaded_isr()
1903 		else if (ctx->reg_int & mask_ce)  in thunderx_l2c_threaded_isr()