Lines Matching refs:pvt
316 u64 (*get_tolm)(struct sbridge_pvt *pvt);
317 u64 (*get_tohm)(struct sbridge_pvt *pvt);
326 u8 (*get_node_id)(struct sbridge_pvt *pvt);
328 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
329 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
792 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) in sbridge_get_tolm() argument
797 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
801 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) in sbridge_get_tohm() argument
805 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
809 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) in ibridge_get_tolm() argument
813 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
818 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) in ibridge_get_tohm() argument
822 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
875 static enum mem_type get_memory_type(struct sbridge_pvt *pvt) in get_memory_type() argument
880 if (pvt->pci_ddrio) { in get_memory_type()
881 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, in get_memory_type()
894 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) in haswell_get_memory_type() argument
900 if (!pvt->pci_ddrio) in haswell_get_memory_type()
903 pci_read_config_dword(pvt->pci_ddrio, in haswell_get_memory_type()
909 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
926 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr) in knl_get_width() argument
932 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) in sbridge_get_width() argument
960 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) in ibridge_get_width() argument
969 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) in broadwell_get_width() argument
975 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt) in knl_get_memory_type() argument
981 static u8 get_node_id(struct sbridge_pvt *pvt) in get_node_id() argument
984 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
988 static u8 haswell_get_node_id(struct sbridge_pvt *pvt) in haswell_get_node_id() argument
992 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
996 static u8 knl_get_node_id(struct sbridge_pvt *pvt) in knl_get_node_id() argument
1000 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in knl_get_node_id()
1038 static u64 haswell_get_tolm(struct sbridge_pvt *pvt) in haswell_get_tolm() argument
1042 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
1046 static u64 haswell_get_tohm(struct sbridge_pvt *pvt) in haswell_get_tohm() argument
1051 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
1053 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
1059 static u64 knl_get_tolm(struct sbridge_pvt *pvt) in knl_get_tolm() argument
1063 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); in knl_get_tolm()
1067 static u64 knl_get_tohm(struct sbridge_pvt *pvt) in knl_get_tohm() argument
1072 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); in knl_get_tohm()
1073 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); in knl_get_tohm()
1147 static int knl_get_tad(const struct sbridge_pvt *pvt, in knl_get_tad() argument
1160 pci_mc = pvt->knl.pci_mc0; in knl_get_tad()
1163 pci_mc = pvt->knl.pci_mc1; in knl_get_tad()
1341 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes) in knl_get_dimm_capacity() argument
1368 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1394 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1417 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { in knl_get_dimm_capacity()
1421 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1422 pvt->info.dram_rule[sad_rule], &dram_rule); in knl_get_dimm_capacity()
1429 sad_limit = pvt->info.sad_limit(dram_rule)+1; in knl_get_dimm_capacity()
1432 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1433 pvt->info.interleave_list[sad_rule], &interleave_reg); in knl_get_dimm_capacity()
1439 first_pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1442 pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1486 if (knl_get_tad(pvt, in knl_get_dimm_capacity()
1567 struct sbridge_pvt *pvt = mci->pvt_info; in get_source_id() local
1570 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || in get_source_id()
1571 pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1572 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_source_id()
1574 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_source_id()
1576 if (pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1577 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); in get_source_id()
1579 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_source_id()
1586 struct sbridge_pvt *pvt = mci->pvt_info; in __populate_dimms() local
1587 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS in __populate_dimms()
1594 mtype = pvt->info.get_memory_type(pvt); in __populate_dimms()
1612 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1614 if (!pvt->knl.pci_channel[i]) in __populate_dimms()
1618 if (!pvt->pci_tad[i]) in __populate_dimms()
1624 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1625 pci_read_config_dword(pvt->knl.pci_channel[i], in __populate_dimms()
1628 pci_read_config_dword(pvt->pci_tad[i], in __populate_dimms()
1633 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { in __populate_dimms()
1635 pvt->sbridge_dev->source_id, in __populate_dimms()
1636 pvt->sbridge_dev->dom, i); in __populate_dimms()
1639 pvt->channel[i].dimms++; in __populate_dimms()
1641 ranks = numrank(pvt->info.type, mtr); in __populate_dimms()
1643 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1657 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, in __populate_dimms()
1663 dimm->dtype = pvt->info.get_width(pvt, mtr); in __populate_dimms()
1668 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); in __populate_dimms()
1678 struct sbridge_pvt *pvt = mci->pvt_info; in get_dimm_config() local
1683 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); in get_dimm_config()
1685 pvt->sbridge_dev->mc, in get_dimm_config()
1686 pvt->sbridge_dev->node_id, in get_dimm_config()
1687 pvt->sbridge_dev->source_id); in get_dimm_config()
1692 if (pvt->info.type == KNIGHTS_LANDING) { in get_dimm_config()
1694 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1695 pvt->is_cur_addr_mirrored = false; in get_dimm_config()
1697 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0) in get_dimm_config()
1699 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1704 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_dimm_config()
1705 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { in get_dimm_config()
1709 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); in get_dimm_config()
1711 pvt->mirror_mode = ADDR_RANGE_MIRRORING; in get_dimm_config()
1716 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { in get_dimm_config()
1721 pvt->mirror_mode = FULL_MIRRORING; in get_dimm_config()
1724 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1729 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1733 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { in get_dimm_config()
1736 pvt->is_lockstep = true; in get_dimm_config()
1740 pvt->is_lockstep = false; in get_dimm_config()
1742 if (IS_CLOSE_PG(pvt->info.mcmtr)) { in get_dimm_config()
1744 pvt->is_close_pg = true; in get_dimm_config()
1747 pvt->is_close_pg = false; in get_dimm_config()
1756 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_layout() local
1768 pvt->tolm = pvt->info.get_tolm(pvt); in get_memory_layout()
1769 tmp_mb = (1 + pvt->tolm) >> 20; in get_memory_layout()
1773 gb, (mb*1000)/1024, (u64)pvt->tolm); in get_memory_layout()
1776 pvt->tohm = pvt->info.get_tohm(pvt); in get_memory_layout()
1777 tmp_mb = (1 + pvt->tohm) >> 20; in get_memory_layout()
1781 gb, (mb*1000)/1024, (u64)pvt->tohm); in get_memory_layout()
1790 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_layout()
1792 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_layout()
1794 limit = pvt->info.sad_limit(reg); in get_memory_layout()
1806 show_dram_attr(pvt->info.dram_attr(reg)), in get_memory_layout()
1809 get_intlv_mode_str(reg, pvt->info.type), in get_memory_layout()
1813 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_layout()
1815 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1817 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1826 if (pvt->info.type == KNIGHTS_LANDING) in get_memory_layout()
1834 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); in get_memory_layout()
1858 if (!pvt->channel[i].dimms) in get_memory_layout()
1861 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1878 if (!pvt->channel[i].dimms) in get_memory_layout()
1881 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1888 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1899 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1902 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1909 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1935 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_error_data() local
1956 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { in get_memory_error_data()
1960 if (addr >= (u64)pvt->tohm) { in get_memory_error_data()
1968 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_error_data()
1969 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_error_data()
1975 limit = pvt->info.sad_limit(reg); in get_memory_error_data()
1984 if (n_sads == pvt->info.max_sad) { in get_memory_error_data()
1989 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); in get_memory_error_data()
1990 interleave_mode = pvt->info.interleave_mode(dram_rule); in get_memory_error_data()
1992 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_error_data()
1995 if (pvt->info.type == SANDY_BRIDGE) { in get_memory_error_data()
1996 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
1998 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
2006 pvt->sbridge_dev->mc, in get_memory_error_data()
2035 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_memory_error_data()
2052 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2058 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
2067 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2087 pvt = mci->pvt_info; in get_memory_error_data()
2093 pci_ha = pvt->pci_ha; in get_memory_error_data()
2117 if (pvt->is_chan_hash) in get_memory_error_data()
2144 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); in get_memory_error_data()
2146 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data()
2147 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { in get_memory_error_data()
2159 pvt->is_cur_addr_mirrored = true; in get_memory_error_data()
2162 pvt->is_cur_addr_mirrored = false; in get_memory_error_data()
2165 if (pvt->is_lockstep) in get_memory_error_data()
2200 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); in get_memory_error_data()
2205 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
2222 if (pvt->is_close_pg) in get_memory_error_data()
2228 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); in get_memory_error_data()
2229 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()
2248 struct sbridge_pvt *pvt; in get_memory_error_data_from_mce() local
2257 pvt = mci->pvt_info; in get_memory_error_data_from_mce()
2258 if (!pvt->info.get_ha) { in get_memory_error_data_from_mce()
2262 *ha = pvt->info.get_ha(m->bank); in get_memory_error_data_from_mce()
2275 pvt = new_mci->pvt_info; in get_memory_error_data_from_mce()
2276 pci_ha = pvt->pci_ha; in get_memory_error_data_from_mce()
2281 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data_from_mce()
2282 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { in get_memory_error_data_from_mce()
2284 pvt->is_cur_addr_mirrored = true; in get_memory_error_data_from_mce()
2286 pvt->is_cur_addr_mirrored = false; in get_memory_error_data_from_mce()
2289 if (pvt->is_lockstep) in get_memory_error_data_from_mce()
2491 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mci_bind_devs() local
2503 pvt->pci_sad0 = pdev; in sbridge_mci_bind_devs()
2506 pvt->pci_sad1 = pdev; in sbridge_mci_bind_devs()
2509 pvt->pci_br0 = pdev; in sbridge_mci_bind_devs()
2512 pvt->pci_ha = pdev; in sbridge_mci_bind_devs()
2515 pvt->pci_ta = pdev; in sbridge_mci_bind_devs()
2518 pvt->pci_ras = pdev; in sbridge_mci_bind_devs()
2526 pvt->pci_tad[id] = pdev; in sbridge_mci_bind_devs()
2531 pvt->pci_ddrio = pdev; in sbridge_mci_bind_devs()
2544 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || in sbridge_mci_bind_devs()
2545 !pvt->pci_ras || !pvt->pci_ta) in sbridge_mci_bind_devs()
2565 struct sbridge_pvt *pvt = mci->pvt_info; in ibridge_mci_bind_devs() local
2578 pvt->pci_ha = pdev; in ibridge_mci_bind_devs()
2582 pvt->pci_ta = pdev; in ibridge_mci_bind_devs()
2586 pvt->pci_ras = pdev; in ibridge_mci_bind_devs()
2598 pvt->pci_tad[id] = pdev; in ibridge_mci_bind_devs()
2603 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2606 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2609 pvt->pci_sad0 = pdev; in ibridge_mci_bind_devs()
2612 pvt->pci_br0 = pdev; in ibridge_mci_bind_devs()
2615 pvt->pci_br1 = pdev; in ibridge_mci_bind_devs()
2628 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || in ibridge_mci_bind_devs()
2629 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) in ibridge_mci_bind_devs()
2651 struct sbridge_pvt *pvt = mci->pvt_info; in haswell_mci_bind_devs() local
2657 if (pvt->info.pci_vtd == NULL) in haswell_mci_bind_devs()
2659 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in haswell_mci_bind_devs()
2670 pvt->pci_sad0 = pdev; in haswell_mci_bind_devs()
2673 pvt->pci_sad1 = pdev; in haswell_mci_bind_devs()
2677 pvt->pci_ha = pdev; in haswell_mci_bind_devs()
2681 pvt->pci_ta = pdev; in haswell_mci_bind_devs()
2685 pvt->pci_ras = pdev; in haswell_mci_bind_devs()
2697 pvt->pci_tad[id] = pdev; in haswell_mci_bind_devs()
2705 if (!pvt->pci_ddrio) in haswell_mci_bind_devs()
2706 pvt->pci_ddrio = pdev; in haswell_mci_bind_devs()
2719 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in haswell_mci_bind_devs()
2720 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in haswell_mci_bind_devs()
2736 struct sbridge_pvt *pvt = mci->pvt_info; in broadwell_mci_bind_devs() local
2742 if (pvt->info.pci_vtd == NULL) in broadwell_mci_bind_devs()
2744 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in broadwell_mci_bind_devs()
2755 pvt->pci_sad0 = pdev; in broadwell_mci_bind_devs()
2758 pvt->pci_sad1 = pdev; in broadwell_mci_bind_devs()
2762 pvt->pci_ha = pdev; in broadwell_mci_bind_devs()
2766 pvt->pci_ta = pdev; in broadwell_mci_bind_devs()
2770 pvt->pci_ras = pdev; in broadwell_mci_bind_devs()
2782 pvt->pci_tad[id] = pdev; in broadwell_mci_bind_devs()
2787 pvt->pci_ddrio = pdev; in broadwell_mci_bind_devs()
2800 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in broadwell_mci_bind_devs()
2801 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in broadwell_mci_bind_devs()
2817 struct sbridge_pvt *pvt = mci->pvt_info; in knl_mci_bind_devs() local
2836 pvt->knl.pci_mc0 = pdev; in knl_mci_bind_devs()
2838 pvt->knl.pci_mc1 = pdev; in knl_mci_bind_devs()
2848 pvt->pci_sad0 = pdev; in knl_mci_bind_devs()
2852 pvt->pci_sad1 = pdev; in knl_mci_bind_devs()
2868 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); in knl_mci_bind_devs()
2870 pvt->knl.pci_cha[devidx] = pdev; in knl_mci_bind_devs()
2893 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); in knl_mci_bind_devs()
2894 pvt->knl.pci_channel[devidx] = pdev; in knl_mci_bind_devs()
2898 pvt->knl.pci_mc_info = pdev; in knl_mci_bind_devs()
2902 pvt->pci_ta = pdev; in knl_mci_bind_devs()
2912 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || in knl_mci_bind_devs()
2913 !pvt->pci_sad0 || !pvt->pci_sad1 || in knl_mci_bind_devs()
2914 !pvt->pci_ta) { in knl_mci_bind_devs()
2919 if (!pvt->knl.pci_channel[i]) { in knl_mci_bind_devs()
2926 if (!pvt->knl.pci_cha[i]) { in knl_mci_bind_devs()
2953 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mce_output_error() local
2976 if (pvt->info.type != SANDY_BRIDGE) in sbridge_mce_output_error()
3027 if (pvt->info.type == KNIGHTS_LANDING) { in sbridge_mce_output_error()
3076 pvt = mci->pvt_info; in sbridge_mce_output_error()
3095 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) in sbridge_mce_output_error()
3203 struct sbridge_pvt *pvt; in sbridge_unregister_mci() local
3212 pvt = mci->pvt_info; in sbridge_unregister_mci()
3230 struct sbridge_pvt *pvt; in sbridge_register_mci() local
3243 sizeof(*pvt)); in sbridge_register_mci()
3251 pvt = mci->pvt_info; in sbridge_register_mci()
3252 memset(pvt, 0, sizeof(*pvt)); in sbridge_register_mci()
3255 pvt->sbridge_dev = sbridge_dev; in sbridge_register_mci()
3266 pvt->info.type = type; in sbridge_register_mci()
3269 pvt->info.rankcfgr = IB_RANK_CFG_A; in sbridge_register_mci()
3270 pvt->info.get_tolm = ibridge_get_tolm; in sbridge_register_mci()
3271 pvt->info.get_tohm = ibridge_get_tohm; in sbridge_register_mci()
3272 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3273 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3274 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3275 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3276 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3277 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3278 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3279 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3280 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3281 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3282 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3283 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3291 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3294 pvt->info.rankcfgr = SB_RANK_CFG_A; in sbridge_register_mci()
3295 pvt->info.get_tolm = sbridge_get_tolm; in sbridge_register_mci()
3296 pvt->info.get_tohm = sbridge_get_tohm; in sbridge_register_mci()
3297 pvt->info.dram_rule = sbridge_dram_rule; in sbridge_register_mci()
3298 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3299 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3300 pvt->info.get_ha = sbridge_get_ha; in sbridge_register_mci()
3301 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3302 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3303 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3304 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3305 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); in sbridge_register_mci()
3306 pvt->info.interleave_list = sbridge_interleave_list; in sbridge_register_mci()
3307 pvt->info.interleave_pkg = sbridge_interleave_pkg; in sbridge_register_mci()
3308 pvt->info.get_width = sbridge_get_width; in sbridge_register_mci()
3316 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3320 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3321 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3322 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3323 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3324 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3325 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3326 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3327 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3328 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3329 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3330 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3331 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3332 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3333 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3341 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3345 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3346 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3347 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3348 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3349 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3350 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3351 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3352 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3353 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3354 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3355 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3356 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3357 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3358 pvt->info.get_width = broadwell_get_width; in sbridge_register_mci()
3366 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3370 pvt->info.get_tolm = knl_get_tolm; in sbridge_register_mci()
3371 pvt->info.get_tohm = knl_get_tohm; in sbridge_register_mci()
3372 pvt->info.dram_rule = knl_dram_rule; in sbridge_register_mci()
3373 pvt->info.get_memory_type = knl_get_memory_type; in sbridge_register_mci()
3374 pvt->info.get_node_id = knl_get_node_id; in sbridge_register_mci()
3375 pvt->info.get_ha = knl_get_ha; in sbridge_register_mci()
3376 pvt->info.rir_limit = NULL; in sbridge_register_mci()
3377 pvt->info.sad_limit = knl_sad_limit; in sbridge_register_mci()
3378 pvt->info.interleave_mode = knl_interleave_mode; in sbridge_register_mci()
3379 pvt->info.dram_attr = dram_attr_knl; in sbridge_register_mci()
3380 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); in sbridge_register_mci()
3381 pvt->info.interleave_list = knl_interleave_list; in sbridge_register_mci()
3382 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3383 pvt->info.get_width = knl_get_width; in sbridge_register_mci()
3390 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()