1938 	int			sad_interl, idx, base_ch;  in get_memory_error_data()  local
2127 		base_ch = TAD_TGT0(reg);  in get_memory_error_data()
2130 		base_ch = TAD_TGT1(reg);  in get_memory_error_data()
2133 		base_ch = TAD_TGT2(reg);  in get_memory_error_data()
2136 		base_ch = TAD_TGT3(reg);  in get_memory_error_data()
2142 	*channel_mask = 1 << base_ch;  in get_memory_error_data()
2144 	pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);  in get_memory_error_data()
2148 		*channel_mask |= 1 << ((base_ch + 2) % 4);  in get_memory_error_data()
2166 		*channel_mask |= 1 << ((base_ch + 1) % 4);  in get_memory_error_data()
2178 		 base_ch,  in get_memory_error_data()
2200 		pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], &reg);  in get_memory_error_data()
2228 	pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], &reg);  in get_memory_error_data()