53 	int dimm;  member
988 	daddr->dimm = 0;  in apl_pmi2mem()
1008 	daddr->dimm = (daddr->rank >= 2) ^ drp[pmiidx].dimmflip;  in dnv_pmi2mem()
1138 			 addr, pmiaddr, daddr->chan, daddr->dimm, daddr->rank, daddr->bank, daddr->row, daddr->col);  in get_memory_error_data()
1208 		 errcode, daddr->chan, daddr->dimm, daddr->rank, daddr->row, daddr->bank, daddr->col);  in pnd2_mce_output_error()
1214 						 m->addr & ~PAGE_MASK, 0, daddr->chan, daddr->dimm, -1, optype, msg);  in pnd2_mce_output_error()
1225 	struct dimm_info *dimm;  in apl_get_dimm_config()  local
1234 		dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0);  in apl_get_dimm_config()
1235 		if (!dimm) {  in apl_get_dimm_config()
1256 		dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));  in apl_get_dimm_config()
1257 		dimm->grain = 32;  in apl_get_dimm_config()
1258 		dimm->dtype = (d->dwid == 0) ? DEV_X8 : DEV_X16;  in apl_get_dimm_config()
1259 		dimm->mtype = MEM_DDR3;  in apl_get_dimm_config()
1260 		dimm->edac_mode = EDAC_SECDED;  in apl_get_dimm_config()
1261 		snprintf(dimm->label, sizeof(dimm->label), "Slice#%d_Chan#%d", i / 2, i % 2);  in apl_get_dimm_config()
1272 	struct dimm_info *dimm;  in dnv_get_dimm_config()  local
1314 			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);  in dnv_get_dimm_config()
1315 			if (!dimm) {  in dnv_get_dimm_config()
1322 			dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));  in dnv_get_dimm_config()
1323 			dimm->grain = 32;  in dnv_get_dimm_config()
1324 			dimm->dtype = dnv_dtypes[j ? d->dimmdwid0 : d->dimmdwid1];  in dnv_get_dimm_config()
1325 			dimm->mtype = memtype;  in dnv_get_dimm_config()
1326 			dimm->edac_mode = EDAC_SECDED;  in dnv_get_dimm_config()
1327 			snprintf(dimm->label, sizeof(dimm->label), "Chan#%d_DIMM#%d", i, j);  in dnv_get_dimm_config()
1466 			 m.addr, daddr.chan, daddr.dimm, daddr.rank, daddr.bank, daddr.row, daddr.col);  in debugfs_u64_set()