729 	if (pvt->umc) {  in determine_edac_cap()
733 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))  in determine_edac_cap()
739 			if (pvt->umc[i].umc_cfg & BIT(12))  in determine_edac_cap()
839 	struct amd64_umc *umc;  in __dump_misc_regs_df()  local
844 		umc = &pvt->umc[i];  in __dump_misc_regs_df()
846 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
847 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
848 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
849 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
856 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
859 				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",  in __dump_misc_regs_df()
860 				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");  in __dump_misc_regs_df()
862 				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");  in __dump_misc_regs_df()
864 				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");  in __dump_misc_regs_df()
866 				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");  in __dump_misc_regs_df()
918 	if (pvt->umc)  in dump_misc_regs()
940 		int umc;  in prep_chip_selects()  local
942 		for_each_umc(umc) {  in prep_chip_selects()
943 			pvt->csels[umc].b_cnt = 4;  in prep_chip_selects()
944 			pvt->csels[umc].m_cnt = 2;  in prep_chip_selects()
961 	int cs, umc;  in read_umc_base_mask()  local
963 	for_each_umc(umc) {  in read_umc_base_mask()
964 		umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;  in read_umc_base_mask()
965 		umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;  in read_umc_base_mask()
967 		for_each_chip_select(cs, umc, pvt) {  in read_umc_base_mask()
968 			base = &pvt->csels[umc].csbases[cs];  in read_umc_base_mask()
969 			base_sec = &pvt->csels[umc].csbases_sec[cs];  in read_umc_base_mask()
976 					 umc, cs, *base, base_reg);  in read_umc_base_mask()
980 					 umc, cs, *base_sec, base_reg_sec);  in read_umc_base_mask()
983 		umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;  in read_umc_base_mask()
984 		umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC;  in read_umc_base_mask()
986 		for_each_chip_select_mask(cs, umc, pvt) {  in read_umc_base_mask()
987 			mask = &pvt->csels[umc].csmasks[cs];  in read_umc_base_mask()
988 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];  in read_umc_base_mask()
995 					 umc, cs, *mask, mask_reg);  in read_umc_base_mask()
999 					 umc, cs, *mask_sec, mask_reg_sec);  in read_umc_base_mask()
1013 	if (pvt->umc)  in read_dct_base_mask()
1106 		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))  in determine_memory_type()
1108 		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))  in determine_memory_type()
1449 		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);  in f17_early_channel_count()
1583 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in f17_addr_mask_to_cs_size()  argument
1611 		addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];  in f17_addr_mask_to_cs_size()
1613 		addr_mask_orig = pvt->csels[umc].csmasks[dimm];  in f17_addr_mask_to_cs_size()
2648 	if (pvt->umc) {  in reserve_mc_sibling_devs()
2697 	if (pvt->umc) {  in free_mc_sibling_devs()
2710 	if (pvt->umc) {  in determine_ecc_sym_sz()
2715 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in determine_ecc_sym_sz()
2716 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {  in determine_ecc_sym_sz()
2719 				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {  in determine_ecc_sym_sz()
2745 	struct amd64_umc *umc;  in __read_mc_regs_df()  local
2752 		umc = &pvt->umc[i];  in __read_mc_regs_df()
2754 		amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);  in __read_mc_regs_df()
2755 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in __read_mc_regs_df()
2756 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in __read_mc_regs_df()
2757 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in __read_mc_regs_df()
2758 		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);  in __read_mc_regs_df()
2787 	if (pvt->umc) {  in read_mc_regs()
2885 	if (!pvt->umc) {  in get_csrow_nr_pages()
2909 	u8 umc, cs;  in init_csrows_df()  local
2924 	for_each_umc(umc) {  in init_csrows_df()
2925 		for_each_chip_select(cs, umc, pvt) {  in init_csrows_df()
2926 			if (!csrow_enabled(cs, umc, pvt))  in init_csrows_df()
2930 			dimm = mci->csrows[cs]->channels[umc]->dimm;  in init_csrows_df()
2935 			dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);  in init_csrows_df()
2959 	if (pvt->umc)  in init_csrows()
3256 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in f17h_determine_edac_ctl_cap()
3257 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);  in f17h_determine_edac_ctl_cap()
3258 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);  in f17h_determine_edac_ctl_cap()
3260 			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));  in f17h_determine_edac_ctl_cap()
3261 			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));  in f17h_determine_edac_ctl_cap()
3289 	if (pvt->umc) {  in setup_mci_misc_attrs()
3444 		pvt->umc = kcalloc(num_umcs, sizeof(struct amd64_umc), GFP_KERNEL);  in init_one_instance()
3445 		if (!pvt->umc) {  in init_one_instance()
3521 		kfree(pvt->umc);  in init_one_instance()
3623 	if (pvt->umc)  in setup_pci_device()