Lines Matching refs:pvt
90 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
94 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
95 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
97 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
114 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
117 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
130 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
142 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
143 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
154 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
171 static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval) in __f17h_set_scrubval() argument
180 pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF); in __f17h_set_scrubval()
181 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1); in __f17h_set_scrubval()
183 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1); in __f17h_set_scrubval()
190 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
218 if (pvt->fam == 0x17 || pvt->fam == 0x18) { in __set_scrub_rate()
219 __f17h_set_scrubval(pvt, scrubval); in __set_scrub_rate()
220 } else if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
221 f15h_select_dct(pvt, 0); in __set_scrub_rate()
222 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
223 f15h_select_dct(pvt, 1); in __set_scrub_rate()
224 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
226 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
237 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
240 if (pvt->fam == 0xf) in set_scrub_rate()
243 if (pvt->fam == 0x15) { in set_scrub_rate()
245 if (pvt->model < 0x10) in set_scrub_rate()
246 f15h_select_dct(pvt, 0); in set_scrub_rate()
248 if (pvt->model == 0x60) in set_scrub_rate()
251 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
256 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
260 switch (pvt->fam) { in get_scrub_rate()
263 if (pvt->model < 0x10) in get_scrub_rate()
264 f15h_select_dct(pvt, 0); in get_scrub_rate()
266 if (pvt->model == 0x60) in get_scrub_rate()
267 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
272 amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); in get_scrub_rate()
274 amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); in get_scrub_rate()
283 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
302 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
314 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
315 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
327 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
335 pvt = mci->pvt_info; in find_mc_by_sys_addr()
342 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
346 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
362 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
370 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
391 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
397 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
398 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
399 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
408 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
409 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
410 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
411 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
426 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
427 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
430 if (pvt->fam == 0x15) in get_cs_base_and_mask()
447 #define for_each_chip_select(i, dct, pvt) \ argument
448 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
450 #define chip_select_base(i, dct, pvt) \ argument
451 pvt->csels[dct].csbases[i]
453 #define for_each_chip_select_mask(i, dct, pvt) \ argument
454 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
465 struct amd64_pvt *pvt; in input_addr_to_csrow() local
469 pvt = mci->pvt_info; in input_addr_to_csrow()
471 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
472 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
475 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
482 pvt->mc_node_id); in input_addr_to_csrow()
488 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
512 struct amd64_pvt *pvt = mci->pvt_info; in amd64_get_dram_hole_info() local
515 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in amd64_get_dram_hole_info()
517 pvt->ext_model, pvt->mc_node_id); in amd64_get_dram_hole_info()
522 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in amd64_get_dram_hole_info()
527 if (!dhar_valid(pvt)) { in amd64_get_dram_hole_info()
529 pvt->mc_node_id); in amd64_get_dram_hole_info()
551 *hole_base = dhar_base(pvt); in amd64_get_dram_hole_info()
554 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in amd64_get_dram_hole_info()
555 : k8_dhar_offset(pvt); in amd64_get_dram_hole_info()
558 pvt->mc_node_id, (unsigned long)*hole_base, in amd64_get_dram_hole_info()
596 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
600 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
652 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
656 pvt = mci->pvt_info; in dram_addr_to_input_addr()
662 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
724 static unsigned long determine_edac_cap(struct amd64_pvt *pvt) in determine_edac_cap() argument
729 if (pvt->umc) { in determine_edac_cap()
733 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
739 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
746 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
750 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
759 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
763 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
764 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
780 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
799 static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in f17_get_cs_mode() argument
803 if (csrow_enabled(2 * dimm, ctrl, pvt)) in f17_get_cs_mode()
806 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
810 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
816 static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes_df() argument
826 cs_mode = f17_get_cs_mode(dimm, ctrl, pvt); in debug_display_dimm_sizes_df()
828 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
829 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
837 static void __dump_misc_regs_df(struct amd64_pvt *pvt) in __dump_misc_regs_df() argument
844 umc = &pvt->umc[i]; in __dump_misc_regs_df()
851 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); in __dump_misc_regs_df()
854 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); in __dump_misc_regs_df()
868 if (pvt->dram_type == MEM_LRDDR4) { in __dump_misc_regs_df()
869 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); in __dump_misc_regs_df()
874 debug_display_dimm_sizes_df(pvt, i); in __dump_misc_regs_df()
878 pvt->dhar, dhar_base(pvt)); in __dump_misc_regs_df()
882 static void __dump_misc_regs(struct amd64_pvt *pvt) in __dump_misc_regs() argument
884 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in __dump_misc_regs()
887 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in __dump_misc_regs()
890 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in __dump_misc_regs()
891 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in __dump_misc_regs()
893 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()
895 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in __dump_misc_regs()
898 pvt->dhar, dhar_base(pvt), in __dump_misc_regs()
899 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in __dump_misc_regs()
900 : f10_dhar_offset(pvt)); in __dump_misc_regs()
902 debug_display_dimm_sizes(pvt, 0); in __dump_misc_regs()
905 if (pvt->fam == 0xf) in __dump_misc_regs()
908 debug_display_dimm_sizes(pvt, 1); in __dump_misc_regs()
911 if (!dct_ganging_enabled(pvt)) in __dump_misc_regs()
912 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in __dump_misc_regs()
916 static void dump_misc_regs(struct amd64_pvt *pvt) in dump_misc_regs() argument
918 if (pvt->umc) in dump_misc_regs()
919 __dump_misc_regs_df(pvt); in dump_misc_regs()
921 __dump_misc_regs(pvt); in dump_misc_regs()
923 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dump_misc_regs()
925 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dump_misc_regs()
931 static void prep_chip_selects(struct amd64_pvt *pvt) in prep_chip_selects() argument
933 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
934 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
935 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
936 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
937 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
938 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
939 } else if (pvt->fam >= 0x17) { in prep_chip_selects()
943 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
944 pvt->csels[umc].m_cnt = 2; in prep_chip_selects()
948 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
949 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
953 static void read_umc_base_mask(struct amd64_pvt *pvt) in read_umc_base_mask() argument
967 for_each_chip_select(cs, umc, pvt) { in read_umc_base_mask()
968 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
969 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
974 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) in read_umc_base_mask()
978 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) in read_umc_base_mask()
986 for_each_chip_select_mask(cs, umc, pvt) { in read_umc_base_mask()
987 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
988 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
993 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) in read_umc_base_mask()
997 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) in read_umc_base_mask()
1007 static void read_dct_base_mask(struct amd64_pvt *pvt) in read_dct_base_mask() argument
1011 prep_chip_selects(pvt); in read_dct_base_mask()
1013 if (pvt->umc) in read_dct_base_mask()
1014 return read_umc_base_mask(pvt); in read_dct_base_mask()
1016 for_each_chip_select(cs, 0, pvt) { in read_dct_base_mask()
1019 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
1020 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
1022 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in read_dct_base_mask()
1026 if (pvt->fam == 0xf) in read_dct_base_mask()
1029 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in read_dct_base_mask()
1031 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1035 for_each_chip_select_mask(cs, 0, pvt) { in read_dct_base_mask()
1038 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
1039 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
1041 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in read_dct_base_mask()
1045 if (pvt->fam == 0xf) in read_dct_base_mask()
1048 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in read_dct_base_mask()
1050 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1055 static void determine_memory_type(struct amd64_pvt *pvt) in determine_memory_type() argument
1059 switch (pvt->fam) { in determine_memory_type()
1061 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
1064 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
1068 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
1071 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
1075 if (pvt->model < 0x60) in determine_memory_type()
1087 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in determine_memory_type()
1088 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
1091 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1092 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
1093 pvt->dram_type = MEM_DDR3; in determine_memory_type()
1095 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
1097 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
1106 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) in determine_memory_type()
1107 pvt->dram_type = MEM_LRDDR4; in determine_memory_type()
1108 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) in determine_memory_type()
1109 pvt->dram_type = MEM_RDDR4; in determine_memory_type()
1111 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1115 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
1116 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
1121 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
1125 static int k8_early_channel_count(struct amd64_pvt *pvt) in k8_early_channel_count() argument
1129 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
1131 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
1134 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
1137 pvt->dclr1 = 0; in k8_early_channel_count()
1143 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
1155 pvt = mci->pvt_info; in get_error_address()
1157 if (pvt->fam == 0xf) { in get_error_address()
1167 if (pvt->fam == 0x15) { in get_error_address()
1176 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1191 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1224 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1232 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1233 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1235 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1238 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1241 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1242 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1245 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1248 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1252 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1254 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1265 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1268 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1270 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1273 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1281 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1305 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1346 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1349 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1351 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1355 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1401 static int f1x_early_channel_count(struct amd64_pvt *pvt) in f1x_early_channel_count() argument
1406 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1425 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1443 static int f17_early_channel_count(struct amd64_pvt *pvt) in f17_early_channel_count() argument
1449 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); in f17_early_channel_count()
1513 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1516 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1520 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1529 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1538 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1542 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1546 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1551 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1571 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
1583 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in f17_addr_mask_to_cs_size() argument
1611 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; in f17_addr_mask_to_cs_size()
1613 addr_mask_orig = pvt->csels[umc].csmasks[dimm]; in f17_addr_mask_to_cs_size()
1640 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
1643 if (pvt->fam == 0xf) in read_dram_ctl_register()
1646 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1648 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1651 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
1653 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
1655 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1658 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1659 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1663 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1664 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
1667 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1674 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
1688 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
1705 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
1708 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1710 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
1719 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
1720 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
1742 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
1749 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
1754 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
1755 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
1756 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
1771 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
1772 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
1787 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
1800 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
1804 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
1805 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
1807 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
1808 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
1828 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
1837 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
1841 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
1842 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
1845 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
1856 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
1860 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
1874 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
1878 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
1880 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
1884 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
1904 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
1913 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
1914 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
1915 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
1918 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
1920 if (dhar_valid(pvt) && in f1x_match_to_this_node()
1921 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
1931 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
1933 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
1939 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1940 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
1944 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
1946 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
1955 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
1956 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
1957 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
1959 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
1960 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
1984 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
1994 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
1995 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
1996 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
1997 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
1999 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2000 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2006 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
2008 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
2009 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
2012 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
2013 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
2021 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
2035 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2036 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); in f15_m30h_match_to_this_node()
2038 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
2078 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2084 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
2106 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
2114 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
2117 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2118 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2122 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
2123 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
2124 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2143 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
2147 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2158 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
2166 static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes() argument
2169 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
2170 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
2172 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
2174 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
2180 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
2181 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
2182 : pvt->dbam0; in debug_display_dimm_sizes()
2183 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in debug_display_dimm_sizes()
2184 pvt->csels[1].csbases : in debug_display_dimm_sizes()
2185 pvt->csels[0].csbases; in debug_display_dimm_sizes()
2187 dbam = pvt->dbam0; in debug_display_dimm_sizes()
2188 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
2206 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2212 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2476 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2479 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2482 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2483 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2486 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2488 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2492 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2545 struct amd64_pvt *pvt; in decode_bus_error() local
2556 pvt = mci->pvt_info; in decode_bus_error()
2568 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2573 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2596 struct amd64_pvt *pvt; in decode_umc_error() local
2604 pvt = mci->pvt_info; in decode_umc_error()
2629 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { in decode_umc_error()
2646 reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) in reserve_mc_sibling_devs() argument
2648 if (pvt->umc) { in reserve_mc_sibling_devs()
2649 pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2650 if (!pvt->F0) { in reserve_mc_sibling_devs()
2655 pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2656 if (!pvt->F6) { in reserve_mc_sibling_devs()
2657 pci_dev_put(pvt->F0); in reserve_mc_sibling_devs()
2658 pvt->F0 = NULL; in reserve_mc_sibling_devs()
2664 edac_dbg(1, "F0: %s\n", pci_name(pvt->F0)); in reserve_mc_sibling_devs()
2665 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2666 edac_dbg(1, "F6: %s\n", pci_name(pvt->F6)); in reserve_mc_sibling_devs()
2672 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2673 if (!pvt->F1) { in reserve_mc_sibling_devs()
2679 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2680 if (!pvt->F2) { in reserve_mc_sibling_devs()
2681 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2682 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2688 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2689 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2690 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2695 static void free_mc_sibling_devs(struct amd64_pvt *pvt) in free_mc_sibling_devs() argument
2697 if (pvt->umc) { in free_mc_sibling_devs()
2698 pci_dev_put(pvt->F0); in free_mc_sibling_devs()
2699 pci_dev_put(pvt->F6); in free_mc_sibling_devs()
2701 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
2702 pci_dev_put(pvt->F2); in free_mc_sibling_devs()
2706 static void determine_ecc_sym_sz(struct amd64_pvt *pvt) in determine_ecc_sym_sz() argument
2708 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2710 if (pvt->umc) { in determine_ecc_sym_sz()
2715 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
2716 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
2717 pvt->ecc_sym_sz = 16; in determine_ecc_sym_sz()
2719 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
2720 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2725 } else if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2728 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2730 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2731 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2734 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2735 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2742 static void __read_mc_regs_df(struct amd64_pvt *pvt) in __read_mc_regs_df() argument
2744 u8 nid = pvt->mc_node_id; in __read_mc_regs_df()
2752 umc = &pvt->umc[i]; in __read_mc_regs_df()
2766 static void read_mc_regs(struct amd64_pvt *pvt) in read_mc_regs() argument
2775 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
2776 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
2781 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
2782 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
2787 if (pvt->umc) { in read_mc_regs()
2788 __read_mc_regs_df(pvt); in read_mc_regs()
2789 amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); in read_mc_regs()
2794 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
2796 read_dram_ctl_register(pvt); in read_mc_regs()
2802 read_dram_base_limit_regs(pvt, range); in read_mc_regs()
2804 rw = dram_rw(pvt, range); in read_mc_regs()
2810 get_dram_base(pvt, range), in read_mc_regs()
2811 get_dram_limit(pvt, range)); in read_mc_regs()
2814 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in read_mc_regs()
2817 dram_intlv_sel(pvt, range), in read_mc_regs()
2818 dram_dst_node(pvt, range)); in read_mc_regs()
2821 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
2822 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
2824 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
2826 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
2827 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
2829 if (!dct_ganging_enabled(pvt)) { in read_mc_regs()
2830 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
2831 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
2835 read_dct_base_mask(pvt); in read_mc_regs()
2837 determine_memory_type(pvt); in read_mc_regs()
2838 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
2840 determine_ecc_sym_sz(pvt); in read_mc_regs()
2842 dump_misc_regs(pvt); in read_mc_regs()
2879 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in get_csrow_nr_pages() argument
2881 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
2885 if (!pvt->umc) { in get_csrow_nr_pages()
2889 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); in get_csrow_nr_pages()
2892 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
2904 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows_df() local
2925 for_each_chip_select(cs, umc, pvt) { in init_csrows_df()
2926 if (!csrow_enabled(cs, umc, pvt)) in init_csrows_df()
2933 pvt->mc_node_id, cs); in init_csrows_df()
2935 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
2936 dimm->mtype = pvt->dram_type; in init_csrows_df()
2951 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows() local
2959 if (pvt->umc) in init_csrows()
2962 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
2964 pvt->nbcfg = val; in init_csrows()
2967 pvt->mc_node_id, val, in init_csrows()
2973 for_each_chip_select(i, 0, pvt) { in init_csrows()
2974 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in init_csrows()
2977 if (pvt->fam != 0xf) in init_csrows()
2978 row_dct1 = !!csrow_enabled(i, 1, pvt); in init_csrows()
2987 pvt->mc_node_id, i); in init_csrows()
2990 nr_pages = get_csrow_nr_pages(pvt, 0, i); in init_csrows()
2995 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
2996 int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); in init_csrows()
3005 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in init_csrows()
3006 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in init_csrows()
3011 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
3013 dimm->mtype = pvt->dram_type; in init_csrows()
3251 f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) in f17h_determine_edac_ctl_cap() argument
3256 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3257 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3258 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3260 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3261 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3284 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs() local
3289 if (pvt->umc) { in setup_mci_misc_attrs()
3290 f17h_determine_edac_ctl_cap(mci, pvt); in setup_mci_misc_attrs()
3292 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
3295 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
3299 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
3302 mci->dev_name = pci_name(pvt->F3); in setup_mci_misc_attrs()
3313 static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
3317 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3318 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3319 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3320 pvt->fam = boot_cpu_data.x86; in per_family_init()
3322 switch (pvt->fam) { in per_family_init()
3325 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
3330 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
3334 if (pvt->model == 0x30) { in per_family_init()
3336 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
3338 } else if (pvt->model == 0x60) { in per_family_init()
3340 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
3345 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
3349 if (pvt->model == 0x30) { in per_family_init()
3351 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
3355 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
3359 if (pvt->model >= 0x10 && pvt->model <= 0x2f) { in per_family_init()
3361 pvt->ops = &family_types[F17_M10H_CPUS].ops; in per_family_init()
3363 } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { in per_family_init()
3365 pvt->ops = &family_types[F17_M30H_CPUS].ops; in per_family_init()
3367 } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { in per_family_init()
3369 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3375 pvt->ops = &family_types[F17_CPUS].ops; in per_family_init()
3377 if (pvt->fam == 0x18) in per_family_init()
3387 (pvt->fam == 0xf ? in per_family_init()
3388 (pvt->ext_model >= K8_REV_F ? "revF or later " in per_family_init()
3390 : ""), pvt->mc_node_id); in per_family_init()
3426 struct amd64_pvt *pvt = NULL; in init_one_instance() local
3431 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in init_one_instance()
3432 if (!pvt) in init_one_instance()
3435 pvt->mc_node_id = nid; in init_one_instance()
3436 pvt->F3 = F3; in init_one_instance()
3439 fam_type = per_family_init(pvt); in init_one_instance()
3443 if (pvt->fam >= 0x17) { in init_one_instance()
3444 pvt->umc = kcalloc(num_umcs, sizeof(struct amd64_umc), GFP_KERNEL); in init_one_instance()
3445 if (!pvt->umc) { in init_one_instance()
3457 err = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2); in init_one_instance()
3461 read_mc_regs(pvt); in init_one_instance()
3469 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
3470 if (pvt->channel_count < 0) in init_one_instance()
3475 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
3487 if (pvt->fam >= 0x17) in init_one_instance()
3497 mci->pvt_info = pvt; in init_one_instance()
3498 mci->pdev = &pvt->F3->dev; in init_one_instance()
3517 free_mc_sibling_devs(pvt); in init_one_instance()
3520 if (pvt->fam >= 0x17) in init_one_instance()
3521 kfree(pvt->umc); in init_one_instance()
3524 kfree(pvt); in init_one_instance()
3584 struct amd64_pvt *pvt; in remove_one_instance() local
3594 pvt = mci->pvt_info; in remove_one_instance()
3598 free_mc_sibling_devs(pvt); in remove_one_instance()
3606 kfree(pvt); in remove_one_instance()
3613 struct amd64_pvt *pvt; in setup_pci_device() local
3622 pvt = mci->pvt_info; in setup_pci_device()
3623 if (pvt->umc) in setup_pci_device()
3624 pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR); in setup_pci_device()
3626 pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); in setup_pci_device()