Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
68 It should be noticed that keeping both GHES and a hardware-driven
81 Support for error detection and correction of DRAM ECC errors on
88 Recent Opterons (Family 10h and later) provide for Memory Error
90 allows the operator/user to inject Uncorrectable and Correctable
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
107 Support for error detection and correction on the AMD 76x
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
121 Support for error detection and correction on the Intel
129 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
143 Support for error detection and correction on the Intel
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
164 Support for error detection and correction on the Intel
171 Support for error detection and correction on the Intel
178 Support for error detection and correction the Intel
185 Support for error detection and correction the Intel
188 and Xeon 55xx processors.
194 Support for error detection and correction on the Intel
201 Support for error detection and correction on the Radisys
208 Support for error detection and correction the Intel
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
229 Support for error detection and correction the Intel
230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
239 Support for error detection and correction the Intel
251 Support for error detection and correction the Intel
260 Support for error detection and correction on the Intel
262 first used on the Apollo Lake platform and Denverton
269 Support for error detection and correction on the Freescale
276 Support for error detection and correction on Freescale memory
283 Support for error detection and correction on the Marvell
284 MV64360 and MV64460 chipsets.
290 Support for error detection and correction on PA Semi
297 Support for error detection and correction on the
308 440SP, 440SPe, 460EX, 460GT and 460SX.
314 Support for error detection and correction on the
323 Support for error detection and correction on the
332 Support for error detection and correction on the
333 IBM CPC925 Bridge and Memory Controller, which is
341 Support for error detection and correction on the
348 Support for error detection and correction on the
355 Support for error detection and correction on the primary caches of
362 Support for error detection and correction on the
369 Support for error detection and correction on the
376 Support for error detection and correction on the
384 Support for error detection and correction on the
386 Coherent Processor Interconnect (CCPI) and L2 cache
393 Support for error detection and correction on the
401 Support for error detection and correction on the
410 Support for error detection and correction on the
418 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the
453 Support for error detection and correction on the
460 Support for error detection and correction on the
467 Support for error detection and correction on the SiFive SoCs.
470 bool "Marvell Armada XP DDR and L2 Cache ECC"
473 Support for error correction and detection on the Marvell Aramada XP
474 DDR RAM and L2 cache controllers.
480 Support for error detection and correction on the Synopsys DDR
487 Support for error detection and correction on the
494 Support for error detection and correction on the
501 Support for error detection and correction on the
504 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
506 of Tag RAM and Data RAM.
508 For debugging issues having to do with stability and overall system
515 Support for error detection and correction on the Aspeed AST 2500 SoC.
524 Support for error detection and correction on the