482 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,  in dma_ctrl_write()  function
491 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);  in dma_ctrl_clr()
497 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);  in dma_ctrl_set()
532 		dma_ctrl_write(chan, reg, addr);  in xilinx_write()
1141 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_vdma_start_transfer()
1227 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);  in xilinx_cdma_start_transfer()
1260 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_cdma_start_transfer()
1301 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1310 			dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,  in xilinx_dma_start_transfer()
1314 				dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,  in xilinx_dma_start_transfer()
1317 				dma_ctrl_write(chan,  in xilinx_dma_start_transfer()
1339 			dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,  in xilinx_dma_start_transfer()
1343 				dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,  in xilinx_dma_start_transfer()
1346 				dma_ctrl_write(chan,  in xilinx_dma_start_transfer()
1364 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_dma_start_transfer()
1480 	dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1493 		dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1949 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_prep_dma_cyclic()
2082 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_terminate_all()
2158 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);  in xilinx_vdma_channel_set_config()