Lines Matching refs:dma_ctrl_read
477 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) in dma_ctrl_read() function
491 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); in dma_ctrl_clr()
497 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); in dma_ctrl_set()
1088 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_start()
1128 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_start_transfer()
1295 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_start_transfer()
1429 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), in xilinx_dma_reset()
1430 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_reset()
1476 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); in xilinx_dma_irq_handler()
1501 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), in xilinx_dma_irq_handler()
1502 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); in xilinx_dma_irq_handler()
1947 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_prep_dma_cyclic()
2071 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_terminate_all()
2080 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_terminate_all()
2115 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2502 if (dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & in xilinx_dma_chan_probe()