Lines Matching full:ecc
228 struct edma_cc *ecc; member
302 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
304 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
307 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
309 __raw_writel(val, ecc->base + offset); in edma_write()
312 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
315 unsigned val = edma_read(ecc, offset); in edma_modify()
319 edma_write(ecc, offset, val); in edma_modify()
322 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
324 unsigned val = edma_read(ecc, offset); in edma_and()
327 edma_write(ecc, offset, val); in edma_and()
330 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
332 unsigned val = edma_read(ecc, offset); in edma_or()
335 edma_write(ecc, offset, val); in edma_or()
338 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, in edma_read_array() argument
341 return edma_read(ecc, offset + (i << 2)); in edma_read_array()
344 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, in edma_write_array() argument
347 edma_write(ecc, offset + (i << 2), val); in edma_write_array()
350 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, in edma_modify_array() argument
353 edma_modify(ecc, offset + (i << 2), and, or); in edma_modify_array()
356 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, in edma_or_array() argument
359 edma_or(ecc, offset + (i << 2), or); in edma_or_array()
362 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, in edma_or_array2() argument
365 edma_or(ecc, offset + ((i * 2 + j) << 2), or); in edma_or_array2()
368 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, in edma_write_array2() argument
371 edma_write(ecc, offset + ((i * 2 + j) << 2), val); in edma_write_array2()
374 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) in edma_shadow0_read() argument
376 return edma_read(ecc, EDMA_SHADOW0 + offset); in edma_shadow0_read()
379 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, in edma_shadow0_read_array() argument
382 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); in edma_shadow0_read_array()
385 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, in edma_shadow0_write() argument
388 edma_write(ecc, EDMA_SHADOW0 + offset, val); in edma_shadow0_write()
391 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() argument
394 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); in edma_shadow0_write_array()
397 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, in edma_param_read() argument
400 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); in edma_param_read()
403 static inline void edma_param_write(struct edma_cc *ecc, int offset, in edma_param_write() argument
406 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); in edma_param_write()
409 static inline void edma_param_modify(struct edma_cc *ecc, int offset, in edma_param_modify() argument
412 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); in edma_param_modify()
415 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, in edma_param_and() argument
418 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); in edma_param_and()
421 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, in edma_param_or() argument
424 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); in edma_param_or()
427 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, in edma_assign_priority_to_queue() argument
432 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); in edma_assign_priority_to_queue()
437 struct edma_cc *ecc = echan->ecc; in edma_set_chmap() local
440 if (ecc->chmap_exist) { in edma_set_chmap()
442 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); in edma_set_chmap()
448 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt() local
454 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_setup_interrupt()
455 edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit); in edma_setup_interrupt()
457 edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit); in edma_setup_interrupt()
464 static void edma_write_slot(struct edma_cc *ecc, unsigned slot, in edma_write_slot() argument
468 if (slot >= ecc->num_slots) in edma_write_slot()
470 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
473 static int edma_read_slot(struct edma_cc *ecc, unsigned slot, in edma_read_slot() argument
477 if (slot >= ecc->num_slots) in edma_read_slot()
479 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
486 * @ecc: pointer to edma_cc struct
499 static int edma_alloc_slot(struct edma_cc *ecc, int slot) in edma_alloc_slot() argument
504 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
509 if (ecc->chmap_exist) in edma_alloc_slot()
512 slot = ecc->num_channels; in edma_alloc_slot()
514 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
515 ecc->num_slots, in edma_alloc_slot()
517 if (slot == ecc->num_slots) in edma_alloc_slot()
519 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
522 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
524 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
528 edma_write_slot(ecc, slot, &dummy_paramset); in edma_alloc_slot()
530 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
533 static void edma_free_slot(struct edma_cc *ecc, unsigned slot) in edma_free_slot() argument
536 if (slot >= ecc->num_slots) in edma_free_slot()
539 edma_write_slot(ecc, slot, &dummy_paramset); in edma_free_slot()
540 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
545 * @ecc: pointer to edma_cc struct
551 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) in edma_link() argument
554 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
558 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
561 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, in edma_link()
567 * @ecc: pointer to edma_cc struct
573 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, in edma_get_position() argument
582 return edma_read(ecc, offs); in edma_get_position()
593 struct edma_cc *ecc = echan->ecc; in edma_start() local
600 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_start()
601 edma_shadow0_read_array(ecc, SH_ESR, idx)); in edma_start()
602 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_start()
605 dev_dbg(ecc->dev, "ER%d %08x\n", idx, in edma_start()
606 edma_shadow0_read_array(ecc, SH_ER, idx)); in edma_start()
608 edma_write_array(ecc, EDMA_ECR, idx, ch_bit); in edma_start()
609 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_start()
611 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_start()
612 edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit); in edma_start()
613 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_start()
614 edma_shadow0_read_array(ecc, SH_EER, idx)); in edma_start()
620 struct edma_cc *ecc = echan->ecc; in edma_stop() local
625 edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit); in edma_stop()
626 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_stop()
627 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_stop()
628 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_stop()
631 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_stop()
633 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_stop()
634 edma_shadow0_read_array(ecc, SH_EER, idx)); in edma_stop()
649 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
659 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
666 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel() local
671 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_trigger_channel()
673 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_trigger_channel()
674 edma_shadow0_read_array(ecc, SH_ESR, idx)); in edma_trigger_channel()
679 struct edma_cc *ecc = echan->ecc; in edma_clean_channel() local
684 dev_dbg(ecc->dev, "EMR%d %08x\n", idx, in edma_clean_channel()
685 edma_read_array(ecc, EDMA_EMR, idx)); in edma_clean_channel()
686 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_clean_channel()
688 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit); in edma_clean_channel()
690 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_clean_channel()
691 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); in edma_clean_channel()
698 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq() local
704 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
705 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
709 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), in edma_assign_channel_eventq()
716 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel() local
720 edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), in edma_alloc_channel()
764 struct edma_cc *ecc = echan->ecc; in edma_execute() local
789 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
814 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
826 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
828 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
829 echan->ecc->dummy_slot); in edma_execute()
1103 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1233 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1350 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1462 struct edma_cc *ecc = data; in dma_irq_handler() local
1468 ctlr = ecc->id; in dma_irq_handler()
1472 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1474 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); in dma_irq_handler()
1476 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); in dma_irq_handler()
1479 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); in dma_irq_handler()
1482 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); in dma_irq_handler()
1496 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1497 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1501 edma_shadow0_write(ecc, SH_IEVAL, 1); in dma_irq_handler()
1507 struct edma_cc *ecc = echan->ecc; in edma_error_handler() local
1517 err = edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1548 static inline bool edma_error_pending(struct edma_cc *ecc) in edma_error_pending() argument
1550 if (edma_read_array(ecc, EDMA_EMR, 0) || in edma_error_pending()
1551 edma_read_array(ecc, EDMA_EMR, 1) || in edma_error_pending()
1552 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) in edma_error_pending()
1561 struct edma_cc *ecc = data; in dma_ccerr_handler() local
1567 ctlr = ecc->id; in dma_ccerr_handler()
1571 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1573 if (!edma_error_pending(ecc)) { in dma_ccerr_handler()
1579 dev_err(ecc->dev, "%s: Error interrupt without error event!\n", in dma_ccerr_handler()
1581 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1590 val = edma_read_array(ecc, EDMA_EMR, j); in dma_ccerr_handler()
1594 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1601 edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); in dma_ccerr_handler()
1603 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()
1605 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1609 val = edma_read(ecc, EDMA_QEMR); in dma_ccerr_handler()
1611 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1613 edma_write(ecc, EDMA_QEMCR, val); in dma_ccerr_handler()
1614 edma_shadow0_write(ecc, SH_QSECR, val); in dma_ccerr_handler()
1617 val = edma_read(ecc, EDMA_CCERR); in dma_ccerr_handler()
1619 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1621 edma_write(ecc, EDMA_CCERRCLR, val); in dma_ccerr_handler()
1624 if (!edma_error_pending(ecc)) in dma_ccerr_handler()
1630 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1638 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources() local
1639 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1645 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1647 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1655 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1682 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1693 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1699 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1752 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1768 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) { in edma_residue()
1769 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1892 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) in edma_dma_init() argument
1894 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1896 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1902 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1903 dev_warn(ecc->dev, in edma_dma_init()
1929 s_ddev->dev = ecc->dev; in edma_dma_init()
1933 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1935 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n"); in edma_dma_init()
1939 ecc->dma_memcpy = m_ddev; in edma_dma_init()
1960 m_ddev->dev = ecc->dev; in edma_dma_init()
1962 } else if (!ecc->legacy_mode) { in edma_dma_init()
1963 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
1967 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
1968 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
1969 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
1970 echan->ecc = ecc; in edma_dma_init()
1985 struct edma_cc *ecc) in edma_setup_from_hw() argument
1992 cccfg = edma_read(ecc, EDMA_CCCFG); in edma_setup_from_hw()
1995 ecc->num_region = BIT(value); in edma_setup_from_hw()
1998 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
2001 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
2004 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
2007 ecc->num_tc = value + 1; in edma_setup_from_hw()
2009 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
2012 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
2013 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
2014 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
2015 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
2016 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
2017 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
2033 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
2038 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2198 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate() local
2203 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2206 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2207 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2217 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2220 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2221 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2222 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2260 struct edma_cc *ecc; in edma_probe() local
2292 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); in edma_probe()
2293 if (!ecc) in edma_probe()
2296 ecc->dev = dev; in edma_probe()
2297 ecc->id = pdev->id; in edma_probe()
2298 ecc->legacy_mode = legacy_mode; in edma_probe()
2300 if (ecc->id < 0) in edma_probe()
2301 ecc->id = 0; in edma_probe()
2312 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2313 if (IS_ERR(ecc->base)) in edma_probe()
2314 return PTR_ERR(ecc->base); in edma_probe()
2316 platform_set_drvdata(pdev, ecc); in edma_probe()
2319 ret = edma_setup_from_hw(dev, info, ecc); in edma_probe()
2324 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2325 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2326 if (!ecc->slave_chans) in edma_probe()
2329 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2331 if (!ecc->slot_inuse) in edma_probe()
2334 ecc->default_queue = info->default_queue; in edma_probe()
2341 bitmap_set(ecc->slot_inuse, rsv_slots[i][0], in edma_probe()
2346 for (i = 0; i < ecc->num_slots; i++) { in edma_probe()
2348 if (!test_bit(i, ecc->slot_inuse)) in edma_probe()
2349 edma_write_slot(ecc, i, &dummy_paramset); in edma_probe()
2368 ecc); in edma_probe()
2373 ecc->ccint = irq; in edma_probe()
2384 ecc); in edma_probe()
2389 ecc->ccerrint = irq; in edma_probe()
2392 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2393 if (ecc->dummy_slot < 0) { in edma_probe()
2395 return ecc->dummy_slot; in edma_probe()
2400 if (!ecc->legacy_mode) { in edma_probe()
2404 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2405 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2406 if (!ecc->tc_list) in edma_probe()
2412 if (ret || i == ecc->num_tc) in edma_probe()
2415 ecc->tc_list[i].node = tc_args.np; in edma_probe()
2416 ecc->tc_list[i].id = i; in edma_probe()
2427 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_probe()
2430 edma_write_array2(ecc, EDMA_DRAE, 0, 0, 0x0); in edma_probe()
2431 edma_write_array2(ecc, EDMA_DRAE, 0, 1, 0x0); in edma_probe()
2432 edma_write_array(ecc, EDMA_QRAE, 0, 0x0); in edma_probe()
2434 ecc->info = info; in edma_probe()
2437 edma_dma_init(ecc, legacy_mode); in edma_probe()
2439 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2441 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2444 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2447 ecc->dma_slave.filter.map = info->slave_map; in edma_probe()
2448 ecc->dma_slave.filter.mapcnt = info->slavecnt; in edma_probe()
2449 ecc->dma_slave.filter.fn = edma_filter_fn; in edma_probe()
2451 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2457 if (ecc->dma_memcpy) { in edma_probe()
2458 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2462 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2468 of_dma_controller_register(node, of_edma_xlate, ecc); in edma_probe()
2475 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2493 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_remove() local
2495 devm_free_irq(dev, ecc->ccint, ecc); in edma_remove()
2496 devm_free_irq(dev, ecc->ccerrint, ecc); in edma_remove()
2498 edma_cleanupp_vchan(&ecc->dma_slave); in edma_remove()
2502 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2503 if (ecc->dma_memcpy) in edma_remove()
2504 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2505 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2513 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_suspend() local
2514 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2517 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2527 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_resume() local
2528 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2533 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset); in edma_pm_resume()
2535 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2539 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_pm_resume()
2542 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2545 edma_or_array2(ecc, EDMA_DRAE, 0, in edma_pm_resume()