600 	struct d40_gen_dmac		  gen_dmac;  member
1649 	struct d40_interrupt_lookup *il = base->gen_dmac.il;  in d40_handle_interrupt()
1650 	u32 il_size = base->gen_dmac.il_size;  in d40_handle_interrupt()
2302 	struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;  in __d40_set_prio_rt()
2979 	if (base->gen_dmac.backup)  in d40_save_restore_registers()
2981 			     base->gen_dmac.backup,  in d40_save_restore_registers()
2982 			base->gen_dmac.backup_size,  in d40_save_restore_registers()
3218 		base->gen_dmac.backup = d40_backup_regs_v4b;  in d40_hw_detect_init()
3219 		base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;  in d40_hw_detect_init()
3220 		base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;  in d40_hw_detect_init()
3221 		base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;  in d40_hw_detect_init()
3222 		base->gen_dmac.realtime_en = D40_DREG_CRSEG1;  in d40_hw_detect_init()
3223 		base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;  in d40_hw_detect_init()
3224 		base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;  in d40_hw_detect_init()
3225 		base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;  in d40_hw_detect_init()
3226 		base->gen_dmac.il = il_v4b;  in d40_hw_detect_init()
3227 		base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);  in d40_hw_detect_init()
3228 		base->gen_dmac.init_reg = dma_init_reg_v4b;  in d40_hw_detect_init()
3229 		base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);  in d40_hw_detect_init()
3232 			base->gen_dmac.backup = d40_backup_regs_v4a;  in d40_hw_detect_init()
3233 			base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;  in d40_hw_detect_init()
3235 		base->gen_dmac.interrupt_en = D40_DREG_PCMIS;  in d40_hw_detect_init()
3236 		base->gen_dmac.interrupt_clear = D40_DREG_PCICR;  in d40_hw_detect_init()
3237 		base->gen_dmac.realtime_en = D40_DREG_RSEG1;  in d40_hw_detect_init()
3238 		base->gen_dmac.realtime_clear = D40_DREG_RCEG1;  in d40_hw_detect_init()
3239 		base->gen_dmac.high_prio_en = D40_DREG_PSEG1;  in d40_hw_detect_init()
3240 		base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;  in d40_hw_detect_init()
3241 		base->gen_dmac.il = il_v4a;  in d40_hw_detect_init()
3242 		base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);  in d40_hw_detect_init()
3243 		base->gen_dmac.init_reg = dma_init_reg_v4a;  in d40_hw_detect_init()
3244 		base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);  in d40_hw_detect_init()
3278 	base->regs_interrupt = kmalloc_array(base->gen_dmac.il_size,  in d40_hw_detect_init()
3327 	struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;  in d40_hw_init()
3328 	u32 reg_size = base->gen_dmac.init_reg_size;  in d40_hw_init()
3363 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);  in d40_hw_init()
3366 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);  in d40_hw_init()
3369 	base->gen_dmac.init_reg = NULL;  in d40_hw_init()
3370 	base->gen_dmac.init_reg_size = 0;  in d40_hw_init()