Lines Matching defs:dw_edma_v0_unroll
46 struct dw_edma_v0_unroll { struct
47 u32 padding_1; /* 0x0f8 */
48 u32 wr_engine_chgroup; /* 0x100 */
49 u32 rd_engine_chgroup; /* 0x104 */
50 u32 wr_engine_hshake_cnt_low; /* 0x108 */
51 u32 wr_engine_hshake_cnt_high; /* 0x10c */
52 u32 padding_2[2]; /* [0x110..0x114] */
53 u32 rd_engine_hshake_cnt_low; /* 0x118 */
54 u32 rd_engine_hshake_cnt_high; /* 0x11c */
55 u32 padding_3[2]; /* [0x120..0x124] */
56 u32 wr_ch0_pwr_en; /* 0x128 */
57 u32 wr_ch1_pwr_en; /* 0x12c */
58 u32 wr_ch2_pwr_en; /* 0x130 */
59 u32 wr_ch3_pwr_en; /* 0x134 */
60 u32 wr_ch4_pwr_en; /* 0x138 */
61 u32 wr_ch5_pwr_en; /* 0x13c */
62 u32 wr_ch6_pwr_en; /* 0x140 */
63 u32 wr_ch7_pwr_en; /* 0x144 */
64 u32 padding_4[8]; /* [0x148..0x164] */
65 u32 rd_ch0_pwr_en; /* 0x168 */
66 u32 rd_ch1_pwr_en; /* 0x16c */
67 u32 rd_ch2_pwr_en; /* 0x170 */
68 u32 rd_ch3_pwr_en; /* 0x174 */
69 u32 rd_ch4_pwr_en; /* 0x178 */
70 u32 rd_ch5_pwr_en; /* 0x18c */
71 u32 rd_ch6_pwr_en; /* 0x180 */
72 u32 rd_ch7_pwr_en; /* 0x184 */
73 u32 padding_5[30]; /* [0x188..0x1fc] */
74 struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; /* [0x200..0x1120] */