175 	bitmap_and(has.bits, want->bits, device->cap_mask.bits,  in __dma_device_satisfies_mask()
228 	if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))  in dma_chan_get()
362 		if (dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dma_issue_pending_all()
400 		if (!dma_has_cap(cap, device->cap_mask) ||  in min_chan()
401 		    dma_has_cap(DMA_PRIVATE, device->cap_mask))  in min_chan()
445 		if (dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dma_channel_rebalance()
473 	if (!(test_bit(DMA_SLAVE, device->cap_mask.bits) ||  in dma_get_slave_caps()
474 	      test_bit(DMA_CYCLIC, device->cap_mask.bits)))  in dma_get_slave_caps()
512 	if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))  in private_candidate()
549 		dma_cap_set(DMA_PRIVATE, device->cap_mask);  in find_candidate()
564 				dma_cap_clear(DMA_PRIVATE, device->cap_mask);  in find_candidate()
587 		dma_cap_set(DMA_PRIVATE, device->cap_mask);  in dma_get_slave_channel()
596 				dma_cap_clear(DMA_PRIVATE, device->cap_mask);  in dma_get_slave_channel()
788 		dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);  in dma_release_channel()
807 		if (dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dmaengine_get()
845 		if (dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dmaengine_put()
861 	if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))  in device_has_all_tx_types()
866 	if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))  in device_has_all_tx_types()
871 	if (!dma_has_cap(DMA_XOR, device->cap_mask))  in device_has_all_tx_types()
875 	if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))  in device_has_all_tx_types()
881 	if (!dma_has_cap(DMA_PQ, device->cap_mask))  in device_has_all_tx_types()
885 	if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))  in device_has_all_tx_types()
922 	if (dma_has_cap(DMA_MEMCPY, device->cap_mask) && !device->device_prep_dma_memcpy) {  in dma_async_device_register()
929 	if (dma_has_cap(DMA_XOR, device->cap_mask) && !device->device_prep_dma_xor) {  in dma_async_device_register()
936 	if (dma_has_cap(DMA_XOR_VAL, device->cap_mask) && !device->device_prep_dma_xor_val) {  in dma_async_device_register()
943 	if (dma_has_cap(DMA_PQ, device->cap_mask) && !device->device_prep_dma_pq) {  in dma_async_device_register()
950 	if (dma_has_cap(DMA_PQ_VAL, device->cap_mask) && !device->device_prep_dma_pq_val) {  in dma_async_device_register()
957 	if (dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset) {  in dma_async_device_register()
964 	if (dma_has_cap(DMA_INTERRUPT, device->cap_mask) && !device->device_prep_dma_interrupt) {  in dma_async_device_register()
971 	if (dma_has_cap(DMA_CYCLIC, device->cap_mask) && !device->device_prep_dma_cyclic) {  in dma_async_device_register()
978 	if (dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && !device->device_prep_interleaved_dma) {  in dma_async_device_register()
1001 		dma_cap_set(DMA_ASYNC_TX, device->cap_mask);  in dma_async_device_register()
1058 	if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dma_async_device_register()
1074 	if (dma_has_cap(DMA_PRIVATE, device->cap_mask))  in dma_async_device_register()