20 static inline u32 qce_read(struct qce_device *qce, u32 offset)  in qce_read()  argument
22 	return readl(qce->base + offset);  in qce_read()
25 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)  in qce_write()  argument
27 	writel(val, qce->base + offset);  in qce_write()
30 static inline void qce_write_array(struct qce_device *qce, u32 offset,  in qce_write_array()  argument
36 		qce_write(qce, offset + i * sizeof(u32), val[i]);  in qce_write_array()
40 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)  in qce_clear_array()  argument
45 		qce_write(qce, offset + i * sizeof(u32), 0);  in qce_clear_array()
140 static u32 qce_config_reg(struct qce_device *qce, int little)  in qce_config_reg()  argument
142 	u32 beats = (qce->burst_size >> 3) - 1;  in qce_config_reg()
143 	u32 pipe_pair = qce->pipe_pair_id;  in qce_config_reg()
189 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,  in qce_xtskey()  argument
198 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);  in qce_xtskey()
202 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);  in qce_xtskey()
205 static void qce_setup_config(struct qce_device *qce)  in qce_setup_config()  argument
210 	config = qce_config_reg(qce, 0);  in qce_setup_config()
213 	qce_write(qce, REG_STATUS, 0);  in qce_setup_config()
214 	qce_write(qce, REG_CONFIG, config);  in qce_setup_config()
217 static inline void qce_crypto_go(struct qce_device *qce)  in qce_crypto_go()  argument
219 	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));  in qce_crypto_go()
229 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ahash()  local
241 	qce_setup_config(qce);  in qce_setup_regs_ahash()
244 		qce_write(qce, REG_AUTH_SEG_CFG, 0);  in qce_setup_regs_ahash()
245 		qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
246 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);  in qce_setup_regs_ahash()
247 		qce_clear_array(qce, REG_AUTH_IV0, 16);  in qce_setup_regs_ahash()
248 		qce_clear_array(qce, REG_AUTH_KEY0, 16);  in qce_setup_regs_ahash()
249 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
258 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,  in qce_setup_regs_ahash()
271 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);  in qce_setup_regs_ahash()
274 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
276 		qce_write_array(qce, REG_AUTH_BYTECNT0,  in qce_setup_regs_ahash()
292 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ahash()
293 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
294 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_ahash()
295 	qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
296 	qce_write(qce, REG_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
299 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ahash()
300 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ahash()
302 	qce_crypto_go(qce);  in qce_setup_regs_ahash()
314 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ablkcipher()  local
323 	qce_setup_config(qce);  in qce_setup_regs_ablkcipher()
333 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ablkcipher()
345 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,  in qce_setup_regs_ablkcipher()
352 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);  in qce_setup_regs_ablkcipher()
360 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);  in qce_setup_regs_ablkcipher()
366 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_ablkcipher()
367 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_ablkcipher()
368 	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);  in qce_setup_regs_ablkcipher()
371 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_ablkcipher()
372 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_ablkcipher()
373 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_ablkcipher()
374 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_ablkcipher()
377 	qce_write(qce, REG_SEG_SIZE, totallen);  in qce_setup_regs_ablkcipher()
380 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ablkcipher()
381 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ablkcipher()
383 	qce_crypto_go(qce);  in qce_setup_regs_ablkcipher()
404 int qce_check_status(struct qce_device *qce, u32 *status)  in qce_check_status()  argument
408 	*status = qce_read(qce, REG_STATUS);  in qce_check_status()
422 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)  in qce_get_version()  argument
426 	val = qce_read(qce, REG_VERSION);  in qce_get_version()