643 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)  in hifn_write_1()  function
673 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_stop_device()
677 	hifn_write_1(dev, HIFN_1_DMA_IER, 0);  in hifn_stop_device()
687 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
695 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);  in hifn_reset_dma()
698 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |  in hifn_reset_dma()
703 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
802 	hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |  in hifn_init_pubrng()
815 		hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);  in hifn_init_pubrng()
817 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_pubrng()
824 	hifn_write_1(dev, HIFN_1_RNG_CONFIG,  in hifn_init_pubrng()
857 	hifn_write_1(dev, HIFN_1_DMA_CNFG,  in hifn_enable_crypto()
863 	hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);  in hifn_enable_crypto()
868 		hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);  in hifn_enable_crypto()
872 	hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);  in hifn_enable_crypto()
949 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
956 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
960 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
982 	hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +  in hifn_init_registers()
984 	hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +  in hifn_init_registers()
986 	hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +  in hifn_init_registers()
988 	hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +  in hifn_init_registers()
993 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1007 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1029 	hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_registers()
1042 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_init_registers()
1094 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_setup_crypto_command()
1221 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);  in hifn_setup_cmd_desc()
1256 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);  in hifn_setup_src_desc()
1283 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);  in hifn_setup_res_desc()
1312 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);  in hifn_setup_dst_desc()
1803 			hifn_write_1(dev, HIFN_1_DMA_CSR, r);  in hifn_work()
1863 	hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);  in hifn_interrupt()
1868 		hifn_write_1(dev, HIFN_1_PUB_STATUS,  in hifn_interrupt()
1881 		hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |  in hifn_interrupt()
1901 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_interrupt()