335 			 int idx)  in cc_fin_result()  argument
343 	hw_desc_init(&desc[idx]);  in cc_fin_result()
344 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_fin_result()
346 	set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize,  in cc_fin_result()
348 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_fin_result()
349 	set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_fin_result()
350 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_fin_result()
351 	set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);  in cc_fin_result()
352 	cc_set_endianity(ctx->hash_mode, &desc[idx]);  in cc_fin_result()
353 	idx++;  in cc_fin_result()
355 	return idx;  in cc_fin_result()
359 		       int idx)  in cc_fin_hmac()  argument
367 	hw_desc_init(&desc[idx]);  in cc_fin_hmac()
368 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_fin_hmac()
369 	set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize,  in cc_fin_hmac()
371 	set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_fin_hmac()
372 	cc_set_endianity(ctx->hash_mode, &desc[idx]);  in cc_fin_hmac()
373 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_fin_hmac()
374 	idx++;  in cc_fin_hmac()
377 	hw_desc_init(&desc[idx]);  in cc_fin_hmac()
378 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_fin_hmac()
379 	set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr,  in cc_fin_hmac()
381 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_fin_hmac()
382 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_fin_hmac()
383 	idx++;  in cc_fin_hmac()
386 	hw_desc_init(&desc[idx]);  in cc_fin_hmac()
387 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_fin_hmac()
388 	set_din_sram(&desc[idx],  in cc_fin_hmac()
391 	set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);  in cc_fin_hmac()
392 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_fin_hmac()
393 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_fin_hmac()
394 	idx++;  in cc_fin_hmac()
397 	hw_desc_init(&desc[idx]);  in cc_fin_hmac()
398 	set_din_no_dma(&desc[idx], 0, 0xfffff0);  in cc_fin_hmac()
399 	set_dout_no_dma(&desc[idx], 0, 0, 1);  in cc_fin_hmac()
400 	idx++;  in cc_fin_hmac()
403 	hw_desc_init(&desc[idx]);  in cc_fin_hmac()
404 	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_fin_hmac()
406 	set_flow_mode(&desc[idx], DIN_HASH);  in cc_fin_hmac()
407 	idx++;  in cc_fin_hmac()
409 	return idx;  in cc_fin_hmac()
427 	int idx = 0;  in cc_hash_digest()  local
462 	hw_desc_init(&desc[idx]);  in cc_hash_digest()
463 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_hash_digest()
465 		set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_hash_digest()
468 		set_din_sram(&desc[idx], larval_digest_addr,  in cc_hash_digest()
471 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_digest()
472 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_hash_digest()
473 	idx++;  in cc_hash_digest()
476 	hw_desc_init(&desc[idx]);  in cc_hash_digest()
477 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_hash_digest()
480 		set_din_type(&desc[idx], DMA_DLLI,  in cc_hash_digest()
484 		set_din_const(&desc[idx], 0, ctx->hash_len);  in cc_hash_digest()
486 			set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);  in cc_hash_digest()
488 			set_cipher_do(&desc[idx], DO_PAD);  in cc_hash_digest()
490 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_digest()
491 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_hash_digest()
492 	idx++;  in cc_hash_digest()
494 	cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx);  in cc_hash_digest()
498 		hw_desc_init(&desc[idx]);  in cc_hash_digest()
499 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_digest()
500 		set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,  in cc_hash_digest()
502 		set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_hash_digest()
503 		set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);  in cc_hash_digest()
504 		set_cipher_do(&desc[idx], DO_PAD);  in cc_hash_digest()
505 		idx++;  in cc_hash_digest()
507 		idx = cc_fin_hmac(desc, req, idx);  in cc_hash_digest()
510 	idx = cc_fin_result(desc, req, idx);  in cc_hash_digest()
512 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_hash_digest()
523 			   struct ahash_req_ctx *state, unsigned int idx)  in cc_restore_hash()  argument
526 	hw_desc_init(&desc[idx]);  in cc_restore_hash()
527 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_restore_hash()
528 	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_restore_hash()
530 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_restore_hash()
531 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_restore_hash()
532 	idx++;  in cc_restore_hash()
535 	hw_desc_init(&desc[idx]);  in cc_restore_hash()
536 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_restore_hash()
537 	set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);  in cc_restore_hash()
538 	set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr,  in cc_restore_hash()
540 	set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_restore_hash()
541 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_restore_hash()
542 	idx++;  in cc_restore_hash()
544 	cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx);  in cc_restore_hash()
546 	return idx;  in cc_restore_hash()
560 	u32 idx = 0;  in cc_hash_update()  local
595 	idx = cc_restore_hash(desc, ctx, state, idx);  in cc_hash_update()
598 	hw_desc_init(&desc[idx]);  in cc_hash_update()
599 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_hash_update()
600 	set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,  in cc_hash_update()
602 	set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_hash_update()
603 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_hash_update()
604 	idx++;  in cc_hash_update()
607 	hw_desc_init(&desc[idx]);  in cc_hash_update()
608 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_hash_update()
609 	set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,  in cc_hash_update()
611 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_hash_update()
612 	set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_hash_update()
613 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);  in cc_hash_update()
614 	idx++;  in cc_hash_update()
616 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_hash_update()
638 	unsigned int idx = 0;  in cc_do_finup()  local
667 	idx = cc_restore_hash(desc, ctx, state, idx);  in cc_do_finup()
670 	hw_desc_init(&desc[idx]);  in cc_do_finup()
671 	set_cipher_do(&desc[idx], DO_PAD);  in cc_do_finup()
672 	set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);  in cc_do_finup()
673 	set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,  in cc_do_finup()
675 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);  in cc_do_finup()
676 	set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_do_finup()
677 	idx++;  in cc_do_finup()
680 		idx = cc_fin_hmac(desc, req, idx);  in cc_do_finup()
682 	idx = cc_fin_result(desc, req, idx);  in cc_do_finup()
684 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_do_finup()
727 	int i, idx = 0, rc = 0;  in cc_hash_setkey()  local
768 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
769 			set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
770 			set_din_sram(&desc[idx], larval_addr,  in cc_hash_setkey()
772 			set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_setkey()
773 			set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_hash_setkey()
774 			idx++;  in cc_hash_setkey()
777 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
778 			set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
779 			set_din_const(&desc[idx], 0, ctx->hash_len);  in cc_hash_setkey()
780 			set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);  in cc_hash_setkey()
781 			set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_setkey()
782 			set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_hash_setkey()
783 			idx++;  in cc_hash_setkey()
785 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
786 			set_din_type(&desc[idx], DMA_DLLI,  in cc_hash_setkey()
789 			set_flow_mode(&desc[idx], DIN_HASH);  in cc_hash_setkey()
790 			idx++;  in cc_hash_setkey()
793 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
794 			set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
795 			set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,  in cc_hash_setkey()
797 			set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_hash_setkey()
798 			set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_hash_setkey()
799 			set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);  in cc_hash_setkey()
800 			cc_set_endianity(ctx->hash_mode, &desc[idx]);  in cc_hash_setkey()
801 			idx++;  in cc_hash_setkey()
803 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
804 			set_din_const(&desc[idx], 0, (blocksize - digestsize));  in cc_hash_setkey()
805 			set_flow_mode(&desc[idx], BYPASS);  in cc_hash_setkey()
806 			set_dout_dlli(&desc[idx],  in cc_hash_setkey()
810 			idx++;  in cc_hash_setkey()
812 			hw_desc_init(&desc[idx]);  in cc_hash_setkey()
813 			set_din_type(&desc[idx], DMA_DLLI,  in cc_hash_setkey()
816 			set_flow_mode(&desc[idx], BYPASS);  in cc_hash_setkey()
817 			set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,  in cc_hash_setkey()
819 			idx++;  in cc_hash_setkey()
822 				hw_desc_init(&desc[idx]);  in cc_hash_setkey()
823 				set_din_const(&desc[idx], 0,  in cc_hash_setkey()
825 				set_flow_mode(&desc[idx], BYPASS);  in cc_hash_setkey()
826 				set_dout_dlli(&desc[idx],  in cc_hash_setkey()
830 				idx++;  in cc_hash_setkey()
834 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
835 		set_din_const(&desc[idx], 0, blocksize);  in cc_hash_setkey()
836 		set_flow_mode(&desc[idx], BYPASS);  in cc_hash_setkey()
837 		set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr),  in cc_hash_setkey()
839 		idx++;  in cc_hash_setkey()
842 	rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);  in cc_hash_setkey()
849 	for (idx = 0, i = 0; i < 2; i++) {  in cc_hash_setkey()
851 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
852 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
853 		set_din_sram(&desc[idx], larval_addr, ctx->inter_digestsize);  in cc_hash_setkey()
854 		set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_setkey()
855 		set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_hash_setkey()
856 		idx++;  in cc_hash_setkey()
859 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
860 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
861 		set_din_const(&desc[idx], 0, ctx->hash_len);  in cc_hash_setkey()
862 		set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_setkey()
863 		set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_hash_setkey()
864 		idx++;  in cc_hash_setkey()
867 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
868 		set_xor_val(&desc[idx], hmac_pad_const[i]);  in cc_hash_setkey()
869 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
870 		set_flow_mode(&desc[idx], S_DIN_to_HASH);  in cc_hash_setkey()
871 		set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);  in cc_hash_setkey()
872 		idx++;  in cc_hash_setkey()
875 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
876 		set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr,  in cc_hash_setkey()
878 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
879 		set_xor_active(&desc[idx]);  in cc_hash_setkey()
880 		set_flow_mode(&desc[idx], DIN_HASH);  in cc_hash_setkey()
881 		idx++;  in cc_hash_setkey()
886 		hw_desc_init(&desc[idx]);  in cc_hash_setkey()
887 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_hash_setkey()
889 			set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,  in cc_hash_setkey()
892 			set_dout_dlli(&desc[idx], ctx->digest_buff_dma_addr,  in cc_hash_setkey()
894 		set_flow_mode(&desc[idx], S_HASH_to_DOUT);  in cc_hash_setkey()
895 		set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_hash_setkey()
896 		idx++;  in cc_hash_setkey()
899 	rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);  in cc_hash_setkey()
924 	unsigned int idx = 0;  in cc_xcbc_setkey()  local
957 	hw_desc_init(&desc[idx]);  in cc_xcbc_setkey()
958 	set_din_type(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr,  in cc_xcbc_setkey()
960 	set_cipher_mode(&desc[idx], DRV_CIPHER_ECB);  in cc_xcbc_setkey()
961 	set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);  in cc_xcbc_setkey()
962 	set_key_size_aes(&desc[idx], keylen);  in cc_xcbc_setkey()
963 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_xcbc_setkey()
964 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_xcbc_setkey()
965 	idx++;  in cc_xcbc_setkey()
967 	hw_desc_init(&desc[idx]);  in cc_xcbc_setkey()
968 	set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE);  in cc_xcbc_setkey()
969 	set_flow_mode(&desc[idx], DIN_AES_DOUT);  in cc_xcbc_setkey()
970 	set_dout_dlli(&desc[idx],  in cc_xcbc_setkey()
973 	idx++;  in cc_xcbc_setkey()
975 	hw_desc_init(&desc[idx]);  in cc_xcbc_setkey()
976 	set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE);  in cc_xcbc_setkey()
977 	set_flow_mode(&desc[idx], DIN_AES_DOUT);  in cc_xcbc_setkey()
978 	set_dout_dlli(&desc[idx],  in cc_xcbc_setkey()
981 	idx++;  in cc_xcbc_setkey()
983 	hw_desc_init(&desc[idx]);  in cc_xcbc_setkey()
984 	set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE);  in cc_xcbc_setkey()
985 	set_flow_mode(&desc[idx], DIN_AES_DOUT);  in cc_xcbc_setkey()
986 	set_dout_dlli(&desc[idx],  in cc_xcbc_setkey()
989 	idx++;  in cc_xcbc_setkey()
991 	rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);  in cc_xcbc_setkey()
1159 	u32 idx = 0;  in cc_mac_update()  local
1188 		cc_setup_xcbc(req, desc, &idx);  in cc_mac_update()
1190 		cc_setup_cmac(req, desc, &idx);  in cc_mac_update()
1192 	cc_set_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx);  in cc_mac_update()
1195 	hw_desc_init(&desc[idx]);  in cc_mac_update()
1196 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_update()
1197 	set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,  in cc_mac_update()
1199 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_mac_update()
1200 	set_flow_mode(&desc[idx], S_AES_to_DOUT);  in cc_mac_update()
1201 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_mac_update()
1202 	idx++;  in cc_mac_update()
1208 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_mac_update()
1225 	int idx = 0;  in cc_mac_final()  local
1268 		hw_desc_init(&desc[idx]);  in cc_mac_final()
1269 		set_cipher_mode(&desc[idx], DRV_CIPHER_ECB);  in cc_mac_final()
1270 		set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT);  in cc_mac_final()
1271 		set_din_type(&desc[idx], DMA_DLLI,  in cc_mac_final()
1274 		set_key_size_aes(&desc[idx], key_len);  in cc_mac_final()
1275 		set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_mac_final()
1276 		set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_mac_final()
1277 		idx++;  in cc_mac_final()
1282 		hw_desc_init(&desc[idx]);  in cc_mac_final()
1283 		set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_mac_final()
1285 		set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,  in cc_mac_final()
1287 		set_flow_mode(&desc[idx], DIN_AES_DOUT);  in cc_mac_final()
1288 		idx++;  in cc_mac_final()
1291 		hw_desc_init(&desc[idx]);  in cc_mac_final()
1292 		set_din_no_dma(&desc[idx], 0, 0xfffff0);  in cc_mac_final()
1293 		set_dout_no_dma(&desc[idx], 0, 0, 1);  in cc_mac_final()
1294 		idx++;  in cc_mac_final()
1298 		cc_setup_xcbc(req, desc, &idx);  in cc_mac_final()
1300 		cc_setup_cmac(req, desc, &idx);  in cc_mac_final()
1303 		hw_desc_init(&desc[idx]);  in cc_mac_final()
1304 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_final()
1305 		set_key_size_aes(&desc[idx], key_len);  in cc_mac_final()
1306 		set_cmac_size0_mode(&desc[idx]);  in cc_mac_final()
1307 		set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_mac_final()
1308 		idx++;  in cc_mac_final()
1310 		cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);  in cc_mac_final()
1312 		hw_desc_init(&desc[idx]);  in cc_mac_final()
1313 		set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE);  in cc_mac_final()
1314 		set_flow_mode(&desc[idx], DIN_AES_DOUT);  in cc_mac_final()
1315 		idx++;  in cc_mac_final()
1319 	hw_desc_init(&desc[idx]);  in cc_mac_final()
1321 	set_dout_dlli(&desc[idx], state->digest_result_dma_addr,  in cc_mac_final()
1323 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_mac_final()
1324 	set_flow_mode(&desc[idx], S_AES_to_DOUT);  in cc_mac_final()
1325 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_mac_final()
1326 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_final()
1327 	idx++;  in cc_mac_final()
1329 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_mac_final()
1347 	int idx = 0;  in cc_mac_finup()  local
1383 		cc_setup_xcbc(req, desc, &idx);  in cc_mac_finup()
1386 		cc_setup_cmac(req, desc, &idx);  in cc_mac_finup()
1390 		hw_desc_init(&desc[idx]);  in cc_mac_finup()
1391 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_finup()
1392 		set_key_size_aes(&desc[idx], key_len);  in cc_mac_finup()
1393 		set_cmac_size0_mode(&desc[idx]);  in cc_mac_finup()
1394 		set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_mac_finup()
1395 		idx++;  in cc_mac_finup()
1397 		cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);  in cc_mac_finup()
1401 	hw_desc_init(&desc[idx]);  in cc_mac_finup()
1403 	set_dout_dlli(&desc[idx], state->digest_result_dma_addr,  in cc_mac_finup()
1405 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_mac_finup()
1406 	set_flow_mode(&desc[idx], S_AES_to_DOUT);  in cc_mac_finup()
1407 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_mac_finup()
1408 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_finup()
1409 	idx++;  in cc_mac_finup()
1411 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_mac_finup()
1431 	unsigned int idx = 0;  in cc_mac_digest()  local
1462 		cc_setup_xcbc(req, desc, &idx);  in cc_mac_digest()
1465 		cc_setup_cmac(req, desc, &idx);  in cc_mac_digest()
1469 		hw_desc_init(&desc[idx]);  in cc_mac_digest()
1470 		set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_digest()
1471 		set_key_size_aes(&desc[idx], key_len);  in cc_mac_digest()
1472 		set_cmac_size0_mode(&desc[idx]);  in cc_mac_digest()
1473 		set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_mac_digest()
1474 		idx++;  in cc_mac_digest()
1476 		cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);  in cc_mac_digest()
1480 	hw_desc_init(&desc[idx]);  in cc_mac_digest()
1481 	set_dout_dlli(&desc[idx], state->digest_result_dma_addr,  in cc_mac_digest()
1483 	set_queue_last_ind(ctx->drvdata, &desc[idx]);  in cc_mac_digest()
1484 	set_flow_mode(&desc[idx], S_AES_to_DOUT);  in cc_mac_digest()
1485 	set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);  in cc_mac_digest()
1486 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_mac_digest()
1487 	set_cipher_mode(&desc[idx], ctx->hw_mode);  in cc_mac_digest()
1488 	idx++;  in cc_mac_digest()
1490 	rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);  in cc_mac_digest()
2127 	unsigned int idx = *seq_size;  in cc_setup_xcbc()  local
2133 	hw_desc_init(&desc[idx]);  in cc_setup_xcbc()
2134 	set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr +  in cc_setup_xcbc()
2137 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_setup_xcbc()
2138 	set_hash_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC, ctx->hash_mode);  in cc_setup_xcbc()
2139 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_xcbc()
2140 	set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);  in cc_setup_xcbc()
2141 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_xcbc()
2142 	idx++;  in cc_setup_xcbc()
2145 	hw_desc_init(&desc[idx]);  in cc_setup_xcbc()
2146 	set_din_type(&desc[idx], DMA_DLLI,  in cc_setup_xcbc()
2149 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);  in cc_setup_xcbc()
2150 	set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);  in cc_setup_xcbc()
2151 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_xcbc()
2152 	set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);  in cc_setup_xcbc()
2153 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_xcbc()
2154 	idx++;  in cc_setup_xcbc()
2157 	hw_desc_init(&desc[idx]);  in cc_setup_xcbc()
2158 	set_din_type(&desc[idx], DMA_DLLI,  in cc_setup_xcbc()
2161 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE2);  in cc_setup_xcbc()
2162 	set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);  in cc_setup_xcbc()
2163 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_xcbc()
2164 	set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);  in cc_setup_xcbc()
2165 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_xcbc()
2166 	idx++;  in cc_setup_xcbc()
2169 	hw_desc_init(&desc[idx]);  in cc_setup_xcbc()
2170 	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_setup_xcbc()
2172 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_setup_xcbc()
2173 	set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);  in cc_setup_xcbc()
2174 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_xcbc()
2175 	set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);  in cc_setup_xcbc()
2176 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_xcbc()
2177 	idx++;  in cc_setup_xcbc()
2178 	*seq_size = idx;  in cc_setup_xcbc()
2184 	unsigned int idx = *seq_size;  in cc_setup_cmac()  local
2190 	hw_desc_init(&desc[idx]);  in cc_setup_cmac()
2191 	set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr,  in cc_setup_cmac()
2194 	set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);  in cc_setup_cmac()
2195 	set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC);  in cc_setup_cmac()
2196 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_cmac()
2197 	set_key_size_aes(&desc[idx], ctx->key_params.keylen);  in cc_setup_cmac()
2198 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_cmac()
2199 	idx++;  in cc_setup_cmac()
2202 	hw_desc_init(&desc[idx]);  in cc_setup_cmac()
2203 	set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,  in cc_setup_cmac()
2205 	set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);  in cc_setup_cmac()
2206 	set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC);  in cc_setup_cmac()
2207 	set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);  in cc_setup_cmac()
2208 	set_key_size_aes(&desc[idx], ctx->key_params.keylen);  in cc_setup_cmac()
2209 	set_flow_mode(&desc[idx], S_DIN_to_AES);  in cc_setup_cmac()
2210 	idx++;  in cc_setup_cmac()
2211 	*seq_size = idx;  in cc_setup_cmac()
2219 	unsigned int idx = *seq_size;  in cc_set_desc()  local
2223 		hw_desc_init(&desc[idx]);  in cc_set_desc()
2224 		set_din_type(&desc[idx], DMA_DLLI,  in cc_set_desc()
2227 		set_flow_mode(&desc[idx], flow_mode);  in cc_set_desc()
2228 		idx++;  in cc_set_desc()
2236 		hw_desc_init(&desc[idx]);  in cc_set_desc()
2237 		set_din_type(&desc[idx], DMA_DLLI,  in cc_set_desc()
2240 		set_dout_sram(&desc[idx], ctx->drvdata->mlli_sram_addr,  in cc_set_desc()
2242 		set_flow_mode(&desc[idx], BYPASS);  in cc_set_desc()
2243 		idx++;  in cc_set_desc()
2245 		hw_desc_init(&desc[idx]);  in cc_set_desc()
2246 		set_din_type(&desc[idx], DMA_MLLI,  in cc_set_desc()
2249 		set_flow_mode(&desc[idx], flow_mode);  in cc_set_desc()
2250 		idx++;  in cc_set_desc()
2253 		set_din_not_last_indication(&desc[(idx - 1)]);  in cc_set_desc()
2255 	*seq_size = idx;  in cc_set_desc()