Lines Matching refs:nitrox_write_csr
30 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
31 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
58 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
60 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
104 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
137 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
143 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
147 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
153 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
171 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
186 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
206 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
229 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
260 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); in enable_nps_core_interrupts()
268 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); in nitrox_config_nps_core_unit()
274 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); in nitrox_config_nps_core_unit()
289 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
293 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); in enable_nps_pkt_interrupts()
320 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
335 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
347 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
369 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
375 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
379 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
385 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
391 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
401 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
406 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
407 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
428 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); in nitrox_config_pom_unit()
432 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); in nitrox_config_pom_unit()
448 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
465 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
468 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
470 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
486 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
494 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
506 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
520 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
545 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
548 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
550 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
553 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
555 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
565 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value); in config_nps_core_vfcfg_mode()
659 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
663 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
673 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()
677 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()