72 	void __iomem *base_addr;  member
113 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
115 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
117 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
125 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
142 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
158 	return (u64)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
196 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
198 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
218 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
220 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
263 			readl_relaxed(ttccs->ttc.base_addr +  in ttc_rate_change_clocksource_cb()
289 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
299 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
309 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
347 	ttccs->ttc.base_addr = base;  in ttc_setup_clocksource()
359 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clocksource()
361 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clocksource()
363 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clocksource()
432 	ttcce->ttc.base_addr = base;  in ttc_setup_clockevent()
449 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clockevent()
451 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clockevent()
452 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clockevent()