40 static void __iomem *tcaddr;  variable
57 		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));  in tc_get_cycles()
58 		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles()
59 	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));  in tc_get_cycles()
67 	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles32()
75 		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_suspend()
76 		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));  in tc_clksrc_suspend()
77 		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_suspend()
78 		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &  in tc_clksrc_suspend()
82 	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);  in tc_clksrc_suspend()
91 		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_resume()
92 		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_resume()
93 		writel(0, tcaddr + ATMEL_TC_REG(i, RA));  in tc_clksrc_resume()
94 		writel(0, tcaddr + ATMEL_TC_REG(i, RB));  in tc_clksrc_resume()
96 		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));  in tc_clksrc_resume()
98 		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));  in tc_clksrc_resume()
101 			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));  in tc_clksrc_resume()
105 	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);  in tc_clksrc_resume()
107 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tc_clksrc_resume()
211 	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_set_periodic()
224 	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));  in tc_next_event()
228 			tcaddr + ATMEL_TC_REG(2, CCR));  in tc_next_event()
315 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_dual_chan()
316 	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
317 	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
318 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
319 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
325 			tcaddr + ATMEL_TC_REG(1, CMR));  in tcb_setup_dual_chan()
326 	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
327 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
330 	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);  in tcb_setup_dual_chan()
332 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_dual_chan()
341 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_single_chan()
342 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
343 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()
346 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_single_chan()
371 	if (tcaddr)  in tcb_clksrc_init()
440 	tcaddr = tc.regs;  in tcb_clksrc_init()
491 	tcaddr = NULL;  in tcb_clksrc_init()