57 		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));  in tc_get_cycles()
58 		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles()
59 	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));  in tc_get_cycles()
67 	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles32()
75 		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_suspend()
76 		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));  in tc_clksrc_suspend()
77 		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_suspend()
78 		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &  in tc_clksrc_suspend()
91 		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_resume()
92 		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_resume()
93 		writel(0, tcaddr + ATMEL_TC_REG(i, RA));  in tc_clksrc_resume()
94 		writel(0, tcaddr + ATMEL_TC_REG(i, RB));  in tc_clksrc_resume()
96 		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));  in tc_clksrc_resume()
98 		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));  in tc_clksrc_resume()
101 			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));  in tc_clksrc_resume()
168 	writel(0xff, regs + ATMEL_TC_REG(2, IDR));  in tc_shutdown()
169 	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));  in tc_shutdown()
188 		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));  in tc_set_oneshot()
189 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_oneshot()
210 		     regs + ATMEL_TC_REG(2, CMR));  in tc_set_periodic()
211 	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_set_periodic()
214 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_periodic()
218 		     ATMEL_TC_REG(2, CCR));  in tc_set_periodic()
224 	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));  in tc_next_event()
228 			tcaddr + ATMEL_TC_REG(2, CCR));  in tc_next_event()
250 	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));  in ch2_irq()
315 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_dual_chan()
316 	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
317 	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
318 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
319 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
325 			tcaddr + ATMEL_TC_REG(1, CMR));  in tcb_setup_dual_chan()
326 	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
327 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
341 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_single_chan()
342 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
343 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()
405 		writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));  in tcb_clksrc_init()