35 	struct sh_tmu_device *tmu;  member
85 		switch (ch->tmu->model) {  in sh_tmu_read()
87 			return ioread8(ch->tmu->mapbase + 2);  in sh_tmu_read()
89 			return ioread8(ch->tmu->mapbase + 4);  in sh_tmu_read()
107 		switch (ch->tmu->model) {  in sh_tmu_write()
109 			return iowrite8(value, ch->tmu->mapbase + 2);  in sh_tmu_write()
111 			return iowrite8(value, ch->tmu->mapbase + 4);  in sh_tmu_write()
128 	raw_spin_lock_irqsave(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
137 	raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
145 	ret = clk_enable(ch->tmu->clk);  in __sh_tmu_enable()
147 		dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",  in __sh_tmu_enable()
173 	pm_runtime_get_sync(&ch->tmu->pdev->dev);  in sh_tmu_enable()
174 	dev_pm_syscore_device(&ch->tmu->pdev->dev, true);  in sh_tmu_enable()
188 	clk_disable(ch->tmu->clk);  in __sh_tmu_disable()
201 	dev_pm_syscore_device(&ch->tmu->pdev->dev, false);  in sh_tmu_disable()
202 	pm_runtime_put(&ch->tmu->pdev->dev);  in sh_tmu_disable()
291 		pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_suspend()
303 		pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_resume()
323 	dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",  in sh_tmu_register_clocksource()
326 	clocksource_register_hz(cs, ch->tmu->rate);  in sh_tmu_register_clocksource()
340 		ch->periodic = (ch->tmu->rate + HZ/2) / HZ;  in sh_tmu_clock_event_start()
363 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",  in sh_tmu_clock_event_set_state()
393 	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);  in sh_tmu_clock_event_suspend()
398 	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);  in sh_tmu_clock_event_resume()
419 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",  in sh_tmu_register_clockevent()
422 	clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);  in sh_tmu_register_clockevent()
426 			  dev_name(&ch->tmu->pdev->dev), ch);  in sh_tmu_register_clockevent()
428 		dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_tmu_register_clockevent()
438 		ch->tmu->has_clockevent = true;  in sh_tmu_register()
441 		ch->tmu->has_clocksource = true;  in sh_tmu_register()
450 				struct sh_tmu_device *tmu)  in sh_tmu_channel_setup()  argument
456 	ch->tmu = tmu;  in sh_tmu_channel_setup()
459 	if (tmu->model == SH_TMU_SH3)  in sh_tmu_channel_setup()
460 		ch->base = tmu->mapbase + 4 + ch->index * 12;  in sh_tmu_channel_setup()
462 		ch->base = tmu->mapbase + 8 + ch->index * 12;  in sh_tmu_channel_setup()
464 	ch->irq = platform_get_irq(tmu->pdev, index);  in sh_tmu_channel_setup()
471 	return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),  in sh_tmu_channel_setup()
475 static int sh_tmu_map_memory(struct sh_tmu_device *tmu)  in sh_tmu_map_memory()  argument
479 	res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);  in sh_tmu_map_memory()
481 		dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");  in sh_tmu_map_memory()
485 	tmu->mapbase = ioremap_nocache(res->start, resource_size(res));  in sh_tmu_map_memory()
486 	if (tmu->mapbase == NULL)  in sh_tmu_map_memory()
492 static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)  in sh_tmu_parse_dt()  argument
494 	struct device_node *np = tmu->pdev->dev.of_node;  in sh_tmu_parse_dt()
496 	tmu->model = SH_TMU;  in sh_tmu_parse_dt()
497 	tmu->num_channels = 3;  in sh_tmu_parse_dt()
499 	of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);  in sh_tmu_parse_dt()
501 	if (tmu->num_channels != 2 && tmu->num_channels != 3) {  in sh_tmu_parse_dt()
502 		dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",  in sh_tmu_parse_dt()
503 			tmu->num_channels);  in sh_tmu_parse_dt()
510 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)  in sh_tmu_setup()  argument
515 	tmu->pdev = pdev;  in sh_tmu_setup()
517 	raw_spin_lock_init(&tmu->lock);  in sh_tmu_setup()
520 		ret = sh_tmu_parse_dt(tmu);  in sh_tmu_setup()
527 		tmu->model = id->driver_data;  in sh_tmu_setup()
528 		tmu->num_channels = hweight8(cfg->channels_mask);  in sh_tmu_setup()
530 		dev_err(&tmu->pdev->dev, "missing platform data\n");  in sh_tmu_setup()
535 	tmu->clk = clk_get(&tmu->pdev->dev, "fck");  in sh_tmu_setup()
536 	if (IS_ERR(tmu->clk)) {  in sh_tmu_setup()
537 		dev_err(&tmu->pdev->dev, "cannot get clock\n");  in sh_tmu_setup()
538 		return PTR_ERR(tmu->clk);  in sh_tmu_setup()
541 	ret = clk_prepare(tmu->clk);  in sh_tmu_setup()
546 	ret = clk_enable(tmu->clk);  in sh_tmu_setup()
550 	tmu->rate = clk_get_rate(tmu->clk) / 4;  in sh_tmu_setup()
551 	clk_disable(tmu->clk);  in sh_tmu_setup()
554 	ret = sh_tmu_map_memory(tmu);  in sh_tmu_setup()
556 		dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");  in sh_tmu_setup()
561 	tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels),  in sh_tmu_setup()
563 	if (tmu->channels == NULL) {  in sh_tmu_setup()
572 	for (i = 0; i < tmu->num_channels; ++i) {  in sh_tmu_setup()
573 		ret = sh_tmu_channel_setup(&tmu->channels[i], i,  in sh_tmu_setup()
574 					   i == 0, i == 1, tmu);  in sh_tmu_setup()
579 	platform_set_drvdata(pdev, tmu);  in sh_tmu_setup()
584 	kfree(tmu->channels);  in sh_tmu_setup()
585 	iounmap(tmu->mapbase);  in sh_tmu_setup()
587 	clk_unprepare(tmu->clk);  in sh_tmu_setup()
589 	clk_put(tmu->clk);  in sh_tmu_setup()
595 	struct sh_tmu_device *tmu = platform_get_drvdata(pdev);  in sh_tmu_probe()  local
603 	if (tmu) {  in sh_tmu_probe()
608 	tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);  in sh_tmu_probe()
609 	if (tmu == NULL)  in sh_tmu_probe()
612 	ret = sh_tmu_setup(tmu, pdev);  in sh_tmu_probe()
614 		kfree(tmu);  in sh_tmu_probe()
622 	if (tmu->has_clockevent || tmu->has_clocksource)  in sh_tmu_probe()