80 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)  in sh_tmu_read()  argument
85 		switch (ch->tmu->model) {  in sh_tmu_read()
87 			return ioread8(ch->tmu->mapbase + 2);  in sh_tmu_read()
89 			return ioread8(ch->tmu->mapbase + 4);  in sh_tmu_read()
96 		return ioread16(ch->base + offs);  in sh_tmu_read()
98 		return ioread32(ch->base + offs);  in sh_tmu_read()
101 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,  in sh_tmu_write()  argument
107 		switch (ch->tmu->model) {  in sh_tmu_write()
109 			return iowrite8(value, ch->tmu->mapbase + 2);  in sh_tmu_write()
111 			return iowrite8(value, ch->tmu->mapbase + 4);  in sh_tmu_write()
118 		iowrite16(value, ch->base + offs);  in sh_tmu_write()
120 		iowrite32(value, ch->base + offs);  in sh_tmu_write()
123 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)  in sh_tmu_start_stop_ch()  argument
128 	raw_spin_lock_irqsave(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
129 	value = sh_tmu_read(ch, TSTR);  in sh_tmu_start_stop_ch()
132 		value |= 1 << ch->index;  in sh_tmu_start_stop_ch()
134 		value &= ~(1 << ch->index);  in sh_tmu_start_stop_ch()
136 	sh_tmu_write(ch, TSTR, value);  in sh_tmu_start_stop_ch()
137 	raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
140 static int __sh_tmu_enable(struct sh_tmu_channel *ch)  in __sh_tmu_enable()  argument
145 	ret = clk_enable(ch->tmu->clk);  in __sh_tmu_enable()
147 		dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",  in __sh_tmu_enable()
148 			ch->index);  in __sh_tmu_enable()
153 	sh_tmu_start_stop_ch(ch, 0);  in __sh_tmu_enable()
156 	sh_tmu_write(ch, TCOR, 0xffffffff);  in __sh_tmu_enable()
157 	sh_tmu_write(ch, TCNT, 0xffffffff);  in __sh_tmu_enable()
160 	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);  in __sh_tmu_enable()
163 	sh_tmu_start_stop_ch(ch, 1);  in __sh_tmu_enable()
168 static int sh_tmu_enable(struct sh_tmu_channel *ch)  in sh_tmu_enable()  argument
170 	if (ch->enable_count++ > 0)  in sh_tmu_enable()
173 	pm_runtime_get_sync(&ch->tmu->pdev->dev);  in sh_tmu_enable()
174 	dev_pm_syscore_device(&ch->tmu->pdev->dev, true);  in sh_tmu_enable()
176 	return __sh_tmu_enable(ch);  in sh_tmu_enable()
179 static void __sh_tmu_disable(struct sh_tmu_channel *ch)  in __sh_tmu_disable()  argument
182 	sh_tmu_start_stop_ch(ch, 0);  in __sh_tmu_disable()
185 	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);  in __sh_tmu_disable()
188 	clk_disable(ch->tmu->clk);  in __sh_tmu_disable()
191 static void sh_tmu_disable(struct sh_tmu_channel *ch)  in sh_tmu_disable()  argument
193 	if (WARN_ON(ch->enable_count == 0))  in sh_tmu_disable()
196 	if (--ch->enable_count > 0)  in sh_tmu_disable()
199 	__sh_tmu_disable(ch);  in sh_tmu_disable()
201 	dev_pm_syscore_device(&ch->tmu->pdev->dev, false);  in sh_tmu_disable()
202 	pm_runtime_put(&ch->tmu->pdev->dev);  in sh_tmu_disable()
205 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,  in sh_tmu_set_next()  argument
209 	sh_tmu_start_stop_ch(ch, 0);  in sh_tmu_set_next()
212 	sh_tmu_read(ch, TCR);  in sh_tmu_set_next()
215 	sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);  in sh_tmu_set_next()
219 		sh_tmu_write(ch, TCOR, delta);  in sh_tmu_set_next()
221 		sh_tmu_write(ch, TCOR, 0xffffffff);  in sh_tmu_set_next()
223 	sh_tmu_write(ch, TCNT, delta);  in sh_tmu_set_next()
226 	sh_tmu_start_stop_ch(ch, 1);  in sh_tmu_set_next()
231 	struct sh_tmu_channel *ch = dev_id;  in sh_tmu_interrupt()  local
234 	if (clockevent_state_oneshot(&ch->ced))  in sh_tmu_interrupt()
235 		sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);  in sh_tmu_interrupt()
237 		sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);  in sh_tmu_interrupt()
240 	ch->ced.event_handler(&ch->ced);  in sh_tmu_interrupt()
251 	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);  in sh_tmu_clocksource_read()  local
253 	return sh_tmu_read(ch, TCNT) ^ 0xffffffff;  in sh_tmu_clocksource_read()
258 	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);  in sh_tmu_clocksource_enable()  local
261 	if (WARN_ON(ch->cs_enabled))  in sh_tmu_clocksource_enable()
264 	ret = sh_tmu_enable(ch);  in sh_tmu_clocksource_enable()
266 		ch->cs_enabled = true;  in sh_tmu_clocksource_enable()
273 	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);  in sh_tmu_clocksource_disable()  local
275 	if (WARN_ON(!ch->cs_enabled))  in sh_tmu_clocksource_disable()
278 	sh_tmu_disable(ch);  in sh_tmu_clocksource_disable()
279 	ch->cs_enabled = false;  in sh_tmu_clocksource_disable()
284 	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);  in sh_tmu_clocksource_suspend()  local
286 	if (!ch->cs_enabled)  in sh_tmu_clocksource_suspend()
289 	if (--ch->enable_count == 0) {  in sh_tmu_clocksource_suspend()
290 		__sh_tmu_disable(ch);  in sh_tmu_clocksource_suspend()
291 		pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_suspend()
297 	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);  in sh_tmu_clocksource_resume()  local
299 	if (!ch->cs_enabled)  in sh_tmu_clocksource_resume()
302 	if (ch->enable_count++ == 0) {  in sh_tmu_clocksource_resume()
303 		pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_resume()
304 		__sh_tmu_enable(ch);  in sh_tmu_clocksource_resume()
308 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,  in sh_tmu_register_clocksource()  argument
311 	struct clocksource *cs = &ch->cs;  in sh_tmu_register_clocksource()
323 	dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",  in sh_tmu_register_clocksource()
324 		 ch->index);  in sh_tmu_register_clocksource()
326 	clocksource_register_hz(cs, ch->tmu->rate);  in sh_tmu_register_clocksource()
335 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)  in sh_tmu_clock_event_start()  argument
337 	sh_tmu_enable(ch);  in sh_tmu_clock_event_start()
340 		ch->periodic = (ch->tmu->rate + HZ/2) / HZ;  in sh_tmu_clock_event_start()
341 		sh_tmu_set_next(ch, ch->periodic, 1);  in sh_tmu_clock_event_start()
347 	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);  in sh_tmu_clock_event_shutdown()  local
350 		sh_tmu_disable(ch);  in sh_tmu_clock_event_shutdown()
357 	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);  in sh_tmu_clock_event_set_state()  local
361 		sh_tmu_disable(ch);  in sh_tmu_clock_event_set_state()
363 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",  in sh_tmu_clock_event_set_state()
364 		 ch->index, periodic ? "periodic" : "oneshot");  in sh_tmu_clock_event_set_state()
365 	sh_tmu_clock_event_start(ch, periodic);  in sh_tmu_clock_event_set_state()
382 	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);  in sh_tmu_clock_event_next()  local
387 	sh_tmu_set_next(ch, delta, 0);  in sh_tmu_clock_event_next()
401 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,  in sh_tmu_register_clockevent()  argument
404 	struct clock_event_device *ced = &ch->ced;  in sh_tmu_register_clockevent()
419 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",  in sh_tmu_register_clockevent()
420 		 ch->index);  in sh_tmu_register_clockevent()
422 	clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);  in sh_tmu_register_clockevent()
424 	ret = request_irq(ch->irq, sh_tmu_interrupt,  in sh_tmu_register_clockevent()
426 			  dev_name(&ch->tmu->pdev->dev), ch);  in sh_tmu_register_clockevent()
428 		dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_tmu_register_clockevent()
429 			ch->index, ch->irq);  in sh_tmu_register_clockevent()
434 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,  in sh_tmu_register()  argument
438 		ch->tmu->has_clockevent = true;  in sh_tmu_register()
439 		sh_tmu_register_clockevent(ch, name);  in sh_tmu_register()
441 		ch->tmu->has_clocksource = true;  in sh_tmu_register()
442 		sh_tmu_register_clocksource(ch, name);  in sh_tmu_register()
448 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,  in sh_tmu_channel_setup()  argument
456 	ch->tmu = tmu;  in sh_tmu_channel_setup()
457 	ch->index = index;  in sh_tmu_channel_setup()
460 		ch->base = tmu->mapbase + 4 + ch->index * 12;  in sh_tmu_channel_setup()
462 		ch->base = tmu->mapbase + 8 + ch->index * 12;  in sh_tmu_channel_setup()
464 	ch->irq = platform_get_irq(tmu->pdev, index);  in sh_tmu_channel_setup()
465 	if (ch->irq < 0)  in sh_tmu_channel_setup()
466 		return ch->irq;  in sh_tmu_channel_setup()
468 	ch->cs_enabled = false;  in sh_tmu_channel_setup()
469 	ch->enable_count = 0;  in sh_tmu_channel_setup()
471 	return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),  in sh_tmu_channel_setup()