152 static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)  in sh_mtu2_read()  argument
157 		return ioread8(ch->mtu->mapbase + 0x280);  in sh_mtu2_read()
162 		return ioread16(ch->base + offs);  in sh_mtu2_read()
164 		return ioread8(ch->base + offs);  in sh_mtu2_read()
167 static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,  in sh_mtu2_write()  argument
173 		return iowrite8(value, ch->mtu->mapbase + 0x280);  in sh_mtu2_write()
178 		iowrite16(value, ch->base + offs);  in sh_mtu2_write()
180 		iowrite8(value, ch->base + offs);  in sh_mtu2_write()
183 static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)  in sh_mtu2_start_stop_ch()  argument
188 	raw_spin_lock_irqsave(&ch->mtu->lock, flags);  in sh_mtu2_start_stop_ch()
189 	value = sh_mtu2_read(ch, TSTR);  in sh_mtu2_start_stop_ch()
192 		value |= 1 << ch->index;  in sh_mtu2_start_stop_ch()
194 		value &= ~(1 << ch->index);  in sh_mtu2_start_stop_ch()
196 	sh_mtu2_write(ch, TSTR, value);  in sh_mtu2_start_stop_ch()
197 	raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);  in sh_mtu2_start_stop_ch()
200 static int sh_mtu2_enable(struct sh_mtu2_channel *ch)  in sh_mtu2_enable()  argument
206 	pm_runtime_get_sync(&ch->mtu->pdev->dev);  in sh_mtu2_enable()
207 	dev_pm_syscore_device(&ch->mtu->pdev->dev, true);  in sh_mtu2_enable()
210 	ret = clk_enable(ch->mtu->clk);  in sh_mtu2_enable()
212 		dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",  in sh_mtu2_enable()
213 			ch->index);  in sh_mtu2_enable()
218 	sh_mtu2_start_stop_ch(ch, 0);  in sh_mtu2_enable()
220 	rate = clk_get_rate(ch->mtu->clk) / 64;  in sh_mtu2_enable()
227 	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);  in sh_mtu2_enable()
228 	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |  in sh_mtu2_enable()
230 	sh_mtu2_write(ch, TGR, periodic);  in sh_mtu2_enable()
231 	sh_mtu2_write(ch, TCNT, 0);  in sh_mtu2_enable()
232 	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);  in sh_mtu2_enable()
233 	sh_mtu2_write(ch, TIER, TIER_TGIEA);  in sh_mtu2_enable()
236 	sh_mtu2_start_stop_ch(ch, 1);  in sh_mtu2_enable()
241 static void sh_mtu2_disable(struct sh_mtu2_channel *ch)  in sh_mtu2_disable()  argument
244 	sh_mtu2_start_stop_ch(ch, 0);  in sh_mtu2_disable()
247 	clk_disable(ch->mtu->clk);  in sh_mtu2_disable()
249 	dev_pm_syscore_device(&ch->mtu->pdev->dev, false);  in sh_mtu2_disable()
250 	pm_runtime_put(&ch->mtu->pdev->dev);  in sh_mtu2_disable()
255 	struct sh_mtu2_channel *ch = dev_id;  in sh_mtu2_interrupt()  local
258 	sh_mtu2_read(ch, TSR);  in sh_mtu2_interrupt()
259 	sh_mtu2_write(ch, TSR, ~TSR_TGFA);  in sh_mtu2_interrupt()
262 	ch->ced.event_handler(&ch->ced);  in sh_mtu2_interrupt()
273 	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);  in sh_mtu2_clock_event_shutdown()  local
276 		sh_mtu2_disable(ch);  in sh_mtu2_clock_event_shutdown()
283 	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);  in sh_mtu2_clock_event_set_periodic()  local
286 		sh_mtu2_disable(ch);  in sh_mtu2_clock_event_set_periodic()
288 	dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n",  in sh_mtu2_clock_event_set_periodic()
289 		 ch->index);  in sh_mtu2_clock_event_set_periodic()
290 	sh_mtu2_enable(ch);  in sh_mtu2_clock_event_set_periodic()
304 static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,  in sh_mtu2_register_clockevent()  argument
307 	struct clock_event_device *ced = &ch->ced;  in sh_mtu2_register_clockevent()
318 	dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",  in sh_mtu2_register_clockevent()
319 		 ch->index);  in sh_mtu2_register_clockevent()
323 static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)  in sh_mtu2_register()  argument
325 	ch->mtu->has_clockevent = true;  in sh_mtu2_register()
326 	sh_mtu2_register_clockevent(ch, name);  in sh_mtu2_register()
335 static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,  in sh_mtu2_setup_channel()  argument
342 	ch->mtu = mtu;  in sh_mtu2_setup_channel()
353 			  dev_name(&ch->mtu->pdev->dev), ch);  in sh_mtu2_setup_channel()
355 		dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_mtu2_setup_channel()
360 	ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index];  in sh_mtu2_setup_channel()
361 	ch->index = index;  in sh_mtu2_setup_channel()
363 	return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));  in sh_mtu2_setup_channel()