87 	struct sh_cmt_device *cmt;  member
237 		return ch->cmt->info->read_control(ch->iostart, 0);  in sh_cmt_read_cmstr()
239 		return ch->cmt->info->read_control(ch->cmt->mapbase, 0);  in sh_cmt_read_cmstr()
245 		ch->cmt->info->write_control(ch->iostart, 0, value);  in sh_cmt_write_cmstr()
247 		ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);  in sh_cmt_write_cmstr()
252 	return ch->cmt->info->read_control(ch->ioctrl, CMCSR);  in sh_cmt_read_cmcsr()
257 	ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);  in sh_cmt_write_cmcsr()
262 	return ch->cmt->info->read_count(ch->ioctrl, CMCNT);  in sh_cmt_read_cmcnt()
267 	ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);  in sh_cmt_write_cmcnt()
272 	ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);  in sh_cmt_write_cmcor()
280 	o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
288 		o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
302 	raw_spin_lock_irqsave(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
311 	raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
318 	pm_runtime_get_sync(&ch->cmt->pdev->dev);  in sh_cmt_enable()
319 	dev_pm_syscore_device(&ch->cmt->pdev->dev, true);  in sh_cmt_enable()
322 	ret = clk_enable(ch->cmt->clk);  in sh_cmt_enable()
324 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",  in sh_cmt_enable()
333 	if (ch->cmt->info->width == 16) {  in sh_cmt_enable()
364 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",  in sh_cmt_enable()
375 	clk_disable(ch->cmt->clk);  in sh_cmt_enable()
390 	clk_disable(ch->cmt->clk);  in sh_cmt_disable()
392 	dev_pm_syscore_device(&ch->cmt->pdev->dev, false);  in sh_cmt_disable()
393 	pm_runtime_put(&ch->cmt->pdev->dev);  in sh_cmt_disable()
483 			dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",  in sh_cmt_clock_event_program_verify()
492 		dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",  in __sh_cmt_set_next()
514 			   ch->cmt->info->clear_bits);  in sh_cmt_interrupt()
657 	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_suspend()
667 	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_resume()
686 	dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",  in sh_cmt_register_clocksource()
689 	clocksource_register_hz(cs, ch->cmt->rate);  in sh_cmt_register_clocksource()
703 		sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);  in sh_cmt_clock_event_start()
725 	dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",  in sh_cmt_clock_event_set_state()
759 	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_suspend()
760 	clk_unprepare(ch->cmt->clk);  in sh_cmt_clock_event_suspend()
767 	clk_prepare(ch->cmt->clk);  in sh_cmt_clock_event_resume()
768 	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_resume()
778 	irq = platform_get_irq(ch->cmt->pdev, ch->index);  in sh_cmt_register_clockevent()
784 			  dev_name(&ch->cmt->pdev->dev), ch);  in sh_cmt_register_clockevent()
786 		dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_cmt_register_clockevent()
805 	ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);  in sh_cmt_register_clockevent()
811 	dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",  in sh_cmt_register_clockevent()
824 		ch->cmt->has_clockevent = true;  in sh_cmt_register()
831 		ch->cmt->has_clocksource = true;  in sh_cmt_register()
840 				bool clocksource, struct sh_cmt_device *cmt)  in sh_cmt_setup_channel()  argument
848 	ch->cmt = cmt;  in sh_cmt_setup_channel()
858 	switch (cmt->info->model) {  in sh_cmt_setup_channel()
860 		ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;  in sh_cmt_setup_channel()
864 		ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;  in sh_cmt_setup_channel()
868 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;  in sh_cmt_setup_channel()
874 	if (cmt->info->width == (sizeof(ch->max_match_value) * 8))  in sh_cmt_setup_channel()
877 		ch->max_match_value = (1 << cmt->info->width) - 1;  in sh_cmt_setup_channel()
882 	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),  in sh_cmt_setup_channel()
885 		dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",  in sh_cmt_setup_channel()
894 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)  in sh_cmt_map_memory()  argument
898 	mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);  in sh_cmt_map_memory()
900 		dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");  in sh_cmt_map_memory()
904 	cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));  in sh_cmt_map_memory()
905 	if (cmt->mapbase == NULL) {  in sh_cmt_map_memory()
906 		dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");  in sh_cmt_map_memory()
959 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)  in sh_cmt_setup()  argument
965 	cmt->pdev = pdev;  in sh_cmt_setup()
966 	raw_spin_lock_init(&cmt->lock);  in sh_cmt_setup()
969 		cmt->info = of_device_get_match_data(&pdev->dev);  in sh_cmt_setup()
970 		cmt->hw_channels = cmt->info->channels_mask;  in sh_cmt_setup()
975 		cmt->info = (const struct sh_cmt_info *)id->driver_data;  in sh_cmt_setup()
976 		cmt->hw_channels = cfg->channels_mask;  in sh_cmt_setup()
978 		dev_err(&cmt->pdev->dev, "missing platform data\n");  in sh_cmt_setup()
983 	cmt->clk = clk_get(&cmt->pdev->dev, "fck");  in sh_cmt_setup()
984 	if (IS_ERR(cmt->clk)) {  in sh_cmt_setup()
985 		dev_err(&cmt->pdev->dev, "cannot get clock\n");  in sh_cmt_setup()
986 		return PTR_ERR(cmt->clk);  in sh_cmt_setup()
989 	ret = clk_prepare(cmt->clk);  in sh_cmt_setup()
994 	ret = clk_enable(cmt->clk);  in sh_cmt_setup()
998 	if (cmt->info->width == 16)  in sh_cmt_setup()
999 		cmt->rate = clk_get_rate(cmt->clk) / 512;  in sh_cmt_setup()
1001 		cmt->rate = clk_get_rate(cmt->clk) / 8;  in sh_cmt_setup()
1003 	clk_disable(cmt->clk);  in sh_cmt_setup()
1006 	ret = sh_cmt_map_memory(cmt);  in sh_cmt_setup()
1011 	cmt->num_channels = hweight8(cmt->hw_channels);  in sh_cmt_setup()
1012 	cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),  in sh_cmt_setup()
1014 	if (cmt->channels == NULL) {  in sh_cmt_setup()
1023 	for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {  in sh_cmt_setup()
1025 		bool clocksource = i == 1 || cmt->num_channels == 1;  in sh_cmt_setup()
1028 		ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,  in sh_cmt_setup()
1029 					   clockevent, clocksource, cmt);  in sh_cmt_setup()
1036 	platform_set_drvdata(pdev, cmt);  in sh_cmt_setup()
1041 	kfree(cmt->channels);  in sh_cmt_setup()
1042 	iounmap(cmt->mapbase);  in sh_cmt_setup()
1044 	clk_unprepare(cmt->clk);  in sh_cmt_setup()
1046 	clk_put(cmt->clk);  in sh_cmt_setup()
1052 	struct sh_cmt_device *cmt = platform_get_drvdata(pdev);  in sh_cmt_probe()  local
1060 	if (cmt) {  in sh_cmt_probe()
1065 	cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);  in sh_cmt_probe()
1066 	if (cmt == NULL)  in sh_cmt_probe()
1069 	ret = sh_cmt_setup(cmt, pdev);  in sh_cmt_probe()
1071 		kfree(cmt);  in sh_cmt_probe()
1079 	if (cmt->has_clockevent || cmt->has_clocksource)  in sh_cmt_probe()