22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
27 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
38 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
43 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
48 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
74 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
97 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
102 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
107 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
112 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
123 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
139 static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
149 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
155 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
166 static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
171 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
176 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
181 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
189 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
196 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
202 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
207 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
226 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
232 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
237 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
242 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
247 static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
252 static const char * const dra7_dss_video1_clk_parents[] __initconst = {
257 static const char * const dra7_dss_video2_clk_parents[] __initconst = {
262 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
272 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
278 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
284 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
289 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {  variable
294 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
301 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
306 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {  variable
311 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
318 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
323 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
328 static const char * const dra7_sata_ref_clk_parents[] __initconst = {
333 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
338 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
343 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
356 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
361 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
366 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
373 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
380 static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
386 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
392 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
401 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
407 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
412 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
427 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
432 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
437 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
442 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
447 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
452 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
457 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
462 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
467 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
472 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
477 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
482 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
487 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
492 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
497 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {  variable
502 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
509 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
514 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {  variable
519 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
526 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
531 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
536 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
541 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
546 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
551 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
586 static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
595 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
601 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
606 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {  variable
611 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
617 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
624 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
630 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
636 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
642 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
648 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
653 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
658 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
663 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
669 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
675 static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
697 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
702 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
707 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
712 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
717 static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
726 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
731 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
736 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
741 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
747 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
752 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
765 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {