Lines Matching refs:TI_CLK_GATE

263 	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
264 	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
265 	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
266 	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
267 	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
268 	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
295 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
312 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
324 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
334 	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
339 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
367 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
368 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
369 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
374 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
375 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
376 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
458 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
468 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
473 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
478 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
483 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
488 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
503 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
520 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
727 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },