Lines Matching refs:TEGRA30_CLK_PLL_P
537 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
803 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
1222 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1223 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1224 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1225 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1226 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1238 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1239 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1240 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1243 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1244 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1245 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1246 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1247 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1248 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1251 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1252 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },