230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)  macro
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
352 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_enable()
359 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_enable()
397 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_disable()
403 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_disable()
413 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
423 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1587 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1602 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1622 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1639 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1647 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1658 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1666 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
2226 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2420 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2437 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2460 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2476 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2501 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2509 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2547 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()