1156 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,  in _pll_fixed_mdiv()  argument
1159 	u16 mdiv = parent_rate / pll_params->cf_min;  in _pll_fixed_mdiv()
1161 	if (pll_params->flags & TEGRA_MDIV_NEW)  in _pll_fixed_mdiv()
1162 		return (!pll_params->mdiv_default ? mdiv :  in _pll_fixed_mdiv()
1163 			min(mdiv, pll_params->mdiv_default));  in _pll_fixed_mdiv()
1165 	if (pll_params->mdiv_default)  in _pll_fixed_mdiv()
1166 		return pll_params->mdiv_default;  in _pll_fixed_mdiv()
1168 	if (parent_rate > pll_params->cf_max)  in _pll_fixed_mdiv()
1221 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,  in _setup_dynamic_ramp()  argument
1250 	val = step_a << pll_params->stepa_shift;  in _setup_dynamic_ramp()
1251 	val |= step_b << pll_params->stepb_shift;  in _setup_dynamic_ramp()
1252 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);  in _setup_dynamic_ramp()
1808 		void __iomem *pmc, struct tegra_clk_pll_params *pll_params,  in _tegra_init_pll()  argument
1820 	pll->params = pll_params;  in _tegra_init_pll()
1823 	if (!pll_params->div_nmp)  in _tegra_init_pll()
1824 		pll_params->div_nmp = &default_nmp;  in _tegra_init_pll()
1860 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pll()  argument
1866 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pll()
1868 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pll()
1891 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle()  argument
1897 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_plle()
1899 	if (!pll_params->div_nmp)  in tegra_clk_register_plle()
1900 		pll_params->div_nmp = &pll_e_nmp;  in tegra_clk_register_plle()
1902 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_plle()
1916 		struct tegra_clk_pll_params *pll_params, spinlock_t *lock)  in tegra_clk_register_pllu()  argument
1921 	pll_params->flags |= TEGRA_PLLU;  in tegra_clk_register_pllu()
1923 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllu()
1983 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllxc()  argument
1998 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllxc()
2003 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
2005 	if (pll_params->adjust_vco)  in tegra_clk_register_pllxc()
2006 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllxc()
2013 	if (!pll_params->set_defaults) {  in tegra_clk_register_pllxc()
2016 		err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);  in tegra_clk_register_pllxc()
2020 		val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllxc()
2021 		val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
2024 			WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));  in tegra_clk_register_pllxc()
2026 			val_iddq |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllxc()
2028 				       clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
2032 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllxc()
2047 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllre()  argument
2054 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
2056 	if (pll_params->adjust_vco)  in tegra_clk_register_pllre()
2057 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre()
2060 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre()
2068 		WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &  in tegra_clk_register_pllre()
2069 				BIT(pll_params->iddq_bit_idx));  in tegra_clk_register_pllre()
2073 		m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllre()
2075 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
2096 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllm()  argument
2103 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllm()
2115 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
2117 	if (pll_params->adjust_vco)  in tegra_clk_register_pllm()
2118 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllm()
2121 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllm()
2122 	pll_params->flags |= TEGRA_PLLM;  in tegra_clk_register_pllm()
2123 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllm()
2138 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllc()  argument
2142 	const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;  in tegra_clk_register_pllc()
2159 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
2161 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllc()
2162 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc()
2175 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
2176 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
2195 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
2196 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
2197 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
2212 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle_tegra114()  argument
2219 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra114()
2226 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2236 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2250 				 struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllu_tegra114()  argument
2256 	pll_params->flags |= TEGRA_PLLU;  in tegra_clk_register_pllu_tegra114()
2258 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllu_tegra114()
2283 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllss()  argument
2293 	if (!pll_params->div_nmp)  in tegra_clk_register_pllss()
2303 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss()
2313 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
2317 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
2318 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
2320 	for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)  in tegra_clk_register_pllss()
2327 	cfg.p = pll_params->pdiv_tohw[i-1].hw_val;  in tegra_clk_register_pllss()
2332 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
2333 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
2334 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
2337 	val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllss()
2339 		if (val_iddq & BIT(pll_params->iddq_bit_idx)) {  in tegra_clk_register_pllss()
2345 		val_iddq |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllss()
2346 		writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllss()
2366 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllre_tegra210()  argument
2372 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre_tegra210()
2374 	if (pll_params->adjust_vco)  in tegra_clk_register_pllre_tegra210()
2375 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre_tegra210()
2378 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre_tegra210()
2533 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle_tegra210()  argument
2540 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra210()
2547 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()
2557 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()
2571 			struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllc_tegra210()  argument
2575 	const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;  in tegra_clk_register_pllc_tegra210()
2591 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc_tegra210()
2593 	if (pll_params->adjust_vco)  in tegra_clk_register_pllc_tegra210()
2594 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllc_tegra210()
2597 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllc_tegra210()
2598 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc_tegra210()
2613 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllss_tegra210()  argument
2621 	if (!pll_params->div_nmp)  in tegra_clk_register_pllss_tegra210()
2631 	val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllss_tegra210()
2639 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss_tegra210()
2641 	if (pll_params->adjust_vco)  in tegra_clk_register_pllss_tegra210()
2642 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllss_tegra210()
2645 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllss_tegra210()
2646 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss_tegra210()
2662 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllmb()  argument
2669 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllmb()
2681 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllmb()
2683 	if (pll_params->adjust_vco)  in tegra_clk_register_pllmb()
2684 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllmb()
2687 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllmb()
2688 	pll_params->flags |= TEGRA_PLLMB;  in tegra_clk_register_pllmb()
2689 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllmb()