Lines Matching refs:periph

15 	struct tegra_clk_periph *periph = to_clk_periph(hw);  in clk_periph_get_parent()  local
16 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_get_parent()
17 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_get_parent()
26 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_set_parent() local
27 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_set_parent()
28 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_set_parent()
38 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_recalc_rate() local
39 const struct clk_ops *div_ops = periph->div_ops; in clk_periph_recalc_rate()
40 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_recalc_rate()
50 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_round_rate() local
51 const struct clk_ops *div_ops = periph->div_ops; in clk_periph_round_rate()
52 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_round_rate()
62 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_set_rate() local
63 const struct clk_ops *div_ops = periph->div_ops; in clk_periph_set_rate()
64 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_set_rate()
73 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_is_enabled() local
74 const struct clk_ops *gate_ops = periph->gate_ops; in clk_periph_is_enabled()
75 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_is_enabled()
84 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_enable() local
85 const struct clk_ops *gate_ops = periph->gate_ops; in clk_periph_enable()
86 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_enable()
95 struct tegra_clk_periph *periph = to_clk_periph(hw); in clk_periph_disable() local
96 const struct clk_ops *gate_ops = periph->gate_ops; in clk_periph_disable()
97 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_disable()
131 struct tegra_clk_periph *periph, in _tegra_clk_register_periph() argument
138 bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); in _tegra_clk_register_periph()
140 if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) { in _tegra_clk_register_periph()
143 } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE) in _tegra_clk_register_periph()
153 bank = get_reg_bank(periph->gate.clk_num); in _tegra_clk_register_periph()
158 periph->hw.init = &init; in _tegra_clk_register_periph()
159 periph->magic = TEGRA_CLK_PERIPH_MAGIC; in _tegra_clk_register_periph()
160 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
161 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
162 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
163 periph->gate.regs = bank; in _tegra_clk_register_periph()
164 periph->gate.enable_refcnt = periph_clk_enb_refcnt; in _tegra_clk_register_periph()
166 clk = clk_register(NULL, &periph->hw); in _tegra_clk_register_periph()
170 periph->mux.hw.clk = clk; in _tegra_clk_register_periph()
171 periph->divider.hw.clk = div ? clk : NULL; in _tegra_clk_register_periph()
172 periph->gate.hw.clk = clk; in _tegra_clk_register_periph()
179 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
183 periph, clk_base, offset, flags); in tegra_clk_register_periph()
188 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
191 periph->gate.flags |= TEGRA_PERIPH_NO_DIV; in tegra_clk_register_periph_nodiv()
193 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
200 init->num_parents, &init->periph, in tegra_clk_register_periph_data()