Lines Matching refs:ENABLE_PCLK_PERIC1
1553 #define ENABLE_PCLK_PERIC1 0x0904 macro
1563 ENABLE_PCLK_PERIC1,
1660 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1662 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1665 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1667 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1669 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1671 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1673 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1675 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1677 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1679 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),