Lines Matching refs:ENABLE_PCLK_AUD
2910 #define ENABLE_PCLK_AUD 0x0900 macro
2924 ENABLE_PCLK_AUD,
2998 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3000 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3002 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3005 ENABLE_PCLK_AUD, 10, 0, 0),
3007 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3009 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3011 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3013 ENABLE_PCLK_AUD, 6, 0, 0),
3015 ENABLE_PCLK_AUD, 5, 0, 0),
3017 ENABLE_PCLK_AUD, 4, 0, 0),
3019 ENABLE_PCLK_AUD, 3, 0, 0),
3020 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3023 ENABLE_PCLK_AUD, 0, 0, 0),