Lines Matching refs:COMPOSITE
379 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
385 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
388 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
401 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
410 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
414 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
417 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
426 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
437 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
443 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
463 COMPOSITE(SCLK_NANDC, "clk_nandc", mux_gpll_cpll_npll_p, 0,
467 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_gpll_cpll_npll_xin24m_p, 0,
471 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_gpll_cpll_npll_xin24m_p, 0,
475 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
497 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_npll_xin24m_p, 0,
508 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
528 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
552 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
562 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
578 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
594 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
609 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
624 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
637 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
650 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
663 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
676 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
689 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
692 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
695 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
698 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
701 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
704 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
707 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
710 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
748 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
751 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
898 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,