28 	struct clk_mux		pll_mux;  member
182 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_set_params()  local
196 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3036_pll_set_params()
198 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3036_pll_set_params()
232 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3036_pll_set_params()
415 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()  local
427 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3066_pll_set_params()
429 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3066_pll_set_params()
465 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3066_pll_set_params()
659 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3399_pll_set_params()  local
673 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);  in rockchip_rk3399_pll_set_params()
675 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);  in rockchip_rk3399_pll_set_params()
711 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);  in rockchip_rk3399_pll_set_params()
842 	struct clk_mux *pll_mux;  in rockchip_clk_register_pll()  local
861 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
862 	pll_mux->reg = ctx->reg_base + mode_offset;  in rockchip_clk_register_pll()
863 	pll_mux->shift = mode_shift;  in rockchip_clk_register_pll()
865 		pll_mux->mask = PLL_RK3328_MODE_MASK;  in rockchip_clk_register_pll()
867 		pll_mux->mask = PLL_MODE_MASK;  in rockchip_clk_register_pll()
868 	pll_mux->flags = 0;  in rockchip_clk_register_pll()
869 	pll_mux->lock = &ctx->lock;  in rockchip_clk_register_pll()
870 	pll_mux->hw.init = &init;  in rockchip_clk_register_pll()
876 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;  in rockchip_clk_register_pll()
892 	mux_clk = clk_register(NULL, &pll_mux->hw);  in rockchip_clk_register_pll()