Lines Matching refs:mult
107 unsigned int mult; in cpg_z_clk_recalc_rate() local
111 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
113 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
122 unsigned int mult; in cpg_z_clk_round_rate() local
125 mult = div_u64(rate * 32ULL, prate); in cpg_z_clk_round_rate()
126 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
128 return (u64)prate * mult / 32; in cpg_z_clk_round_rate()
135 unsigned int mult; in cpg_z_clk_set_rate() local
138 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
140 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
146 ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); in cpg_z_clk_set_rate()
493 rpcd2->fixed.mult = 1; in cpg_rpcd2_clk_register()
545 unsigned int mult = 1; in rcar_gen3_cpg_clk_register() local
566 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
568 mult *= 2; in rcar_gen3_cpg_clk_register()
572 mult = cpg_pll_config->pll1_mult; in rcar_gen3_cpg_clk_register()
584 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
586 mult *= 2; in rcar_gen3_cpg_clk_register()
590 mult = cpg_pll_config->pll3_mult; in rcar_gen3_cpg_clk_register()
602 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen3_cpg_clk_register()
604 mult *= 2; in rcar_gen3_cpg_clk_register()
655 mult = 1; in rcar_gen3_cpg_clk_register()
704 __clk_get_name(parent), 0, mult, div); in rcar_gen3_cpg_clk_register()