Lines Matching refs:mult
57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
63 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
70 unsigned int mult; in cpg_z_clk_round_rate() local
75 mult = div_u64((u64)rate * 32, prate); in cpg_z_clk_round_rate()
76 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
78 return *parent_rate / 32 * mult; in cpg_z_clk_round_rate()
85 unsigned int mult; in cpg_z_clk_set_rate() local
89 mult = div_u64((u64)rate * 32, parent_rate); in cpg_z_clk_set_rate()
90 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
97 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_set_rate()
174 fixed->mult = 1; in cpg_rcan_clk_register()
281 unsigned int mult = 1; in rcar_gen2_cpg_clk_register() local
304 mult = cpg_pll_config->pll0_mult; in rcar_gen2_cpg_clk_register()
306 if (!mult) { in rcar_gen2_cpg_clk_register()
309 mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >> in rcar_gen2_cpg_clk_register()
315 mult = cpg_pll_config->pll1_mult / 2; in rcar_gen2_cpg_clk_register()
319 mult = cpg_pll_config->pll3_mult; in rcar_gen2_cpg_clk_register()
367 0, mult, div); in rcar_gen2_cpg_clk_register()